WAFER LEVEL, CHIP SCALE SEMICONDUCTOR DEVICE PACKAGING COMPOSITION, AND METHOD RELATING THERETO

WAFER LEVEL, CHIP SCALE SEMICONDUCTOR DEVICE PACKAGING COMPOSITION, AND METHOD RELATING THERETO

PROBLEM TO BE SOLVED: To provide wafer level, chip scale semiconductor device packaging compositions capable of providing high density, small scale circuitry lines without the use of photolithography, and a method relating thereto. SOLUTION: The wafer level package comprises a stress buffer layer 10...

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Bibliographische Detailangaben
Hauptverfasser: TSAI BIN-HONG COLIN, LEE YUEH-LING, CHU JAMES, CHEN CHENGUNG, YUN HAO
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Zusammenfassung:PROBLEM TO BE SOLVED: To provide wafer level, chip scale semiconductor device packaging compositions capable of providing high density, small scale circuitry lines without the use of photolithography, and a method relating thereto. SOLUTION: The wafer level package comprises a stress buffer layer 105 containing a polymer binder and a spinel crystal filler in both a non-activated and a laser activated form. The stress buffer layer 105 is patterned with a laser to thereby activate the filler, and the laser ablation path can then be selectively metalized. COPYRIGHT: (C)2010,JPO&INPIT