VIRTUAL TEST SYSTEM CORRESPONDING TO SIMULTANEOUS TEST OF A PLURALITY OF DEVICE UNDER-TESTS (DUT)

PROBLEM TO BE SOLVED: To sufficiently debug an accurate test program. SOLUTION: A virtual test system includes: a plurality of semiconductor operation simulation models 201-1 to 201-32 provided corresponding to a plurality of the device under-tests (DUT); an operation simulation model 101 of an LSI...

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1. Verfasser:	HIKICHI HIROSHI
Format:	Patent
Sprache:	eng
Schlagworte:	MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS TESTING
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creator	HIKICHI HIROSHI
description	PROBLEM TO BE SOLVED: To sufficiently debug an accurate test program. SOLUTION: A virtual test system includes: a plurality of semiconductor operation simulation models 201-1 to 201-32 provided corresponding to a plurality of the device under-tests (DUT); an operation simulation model 101 of an LSI tester for simultaneously testing the plurality of DUTs; and signal delay models 301-1 to 301-32 on a test board mounting the plurality of DUTs. The virtual test system adds the signal delay models 301-1 to 301-32 corresponding to signal lines on the test board to the signal lines connecting the plurality of the semiconductor operation simulation models 201-1 to 201-32 and the operation simulation model 101 of the LSI tester. COPYRIGHT: (C)2010,JPO&INPIT
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fullrecord	<record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JP2010197356A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JP2010197356A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JP2010197356A3</originalsourceid><addsrcrecordid>eNqNyrEKwjAQgOEuDqK-w-GkQ6G1qDiG5qqRNAm5S6FTKRIn0UJ9f6ToAzj9_PDNk75RnoPQwEgM1BJjDaX1HslZI5U5A1sgVQfNwqAN9JW2AgFOBy-04nZaiY0qEYKR6NPJEGxk4O0ymd37xxhXvy6SdYVcXtI4vLo4Dv0tPuO7u7pdlmf56VjsD6L4C30AXOw0cg</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>VIRTUAL TEST SYSTEM CORRESPONDING TO SIMULTANEOUS TEST OF A PLURALITY OF DEVICE UNDER-TESTS (DUT)</title><source>esp@cenet</source><creator>HIKICHI HIROSHI</creator><creatorcontrib>HIKICHI HIROSHI</creatorcontrib><description>PROBLEM TO BE SOLVED: To sufficiently debug an accurate test program. SOLUTION: A virtual test system includes: a plurality of semiconductor operation simulation models 201-1 to 201-32 provided corresponding to a plurality of the device under-tests (DUT); an operation simulation model 101 of an LSI tester for simultaneously testing the plurality of DUTs; and signal delay models 301-1 to 301-32 on a test board mounting the plurality of DUTs. The virtual test system adds the signal delay models 301-1 to 301-32 corresponding to signal lines on the test board to the signal lines connecting the plurality of the semiconductor operation simulation models 201-1 to 201-32 and the operation simulation model 101 of the LSI tester. COPYRIGHT: (C)2010,JPO&INPIT</description><language>eng</language><subject>MEASURING ; MEASURING ELECTRIC VARIABLES ; MEASURING MAGNETIC VARIABLES ; PHYSICS ; TESTING</subject><creationdate>2010</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20100909&DB=EPODOC&CC=JP&NR=2010197356A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20100909&DB=EPODOC&CC=JP&NR=2010197356A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>HIKICHI HIROSHI</creatorcontrib><title>VIRTUAL TEST SYSTEM CORRESPONDING TO SIMULTANEOUS TEST OF A PLURALITY OF DEVICE UNDER-TESTS (DUT)</title><description>PROBLEM TO BE SOLVED: To sufficiently debug an accurate test program. SOLUTION: A virtual test system includes: a plurality of semiconductor operation simulation models 201-1 to 201-32 provided corresponding to a plurality of the device under-tests (DUT); an operation simulation model 101 of an LSI tester for simultaneously testing the plurality of DUTs; and signal delay models 301-1 to 301-32 on a test board mounting the plurality of DUTs. The virtual test system adds the signal delay models 301-1 to 301-32 corresponding to signal lines on the test board to the signal lines connecting the plurality of the semiconductor operation simulation models 201-1 to 201-32 and the operation simulation model 101 of the LSI tester. COPYRIGHT: (C)2010,JPO&INPIT</description><subject>MEASURING</subject><subject>MEASURING ELECTRIC VARIABLES</subject><subject>MEASURING MAGNETIC VARIABLES</subject><subject>PHYSICS</subject><subject>TESTING</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2010</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNyrEKwjAQgOEuDqK-w-GkQ6G1qDiG5qqRNAm5S6FTKRIn0UJ9f6ToAzj9_PDNk75RnoPQwEgM1BJjDaX1HslZI5U5A1sgVQfNwqAN9JW2AgFOBy-04nZaiY0qEYKR6NPJEGxk4O0ymd37xxhXvy6SdYVcXtI4vLo4Dv0tPuO7u7pdlmf56VjsD6L4C30AXOw0cg</recordid><startdate>20100909</startdate><enddate>20100909</enddate><creator>HIKICHI HIROSHI</creator><scope>EVB</scope></search><sort><creationdate>20100909</creationdate><title>VIRTUAL TEST SYSTEM CORRESPONDING TO SIMULTANEOUS TEST OF A PLURALITY OF DEVICE UNDER-TESTS (DUT)</title><author>HIKICHI HIROSHI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2010197356A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2010</creationdate><topic>MEASURING</topic><topic>MEASURING ELECTRIC VARIABLES</topic><topic>MEASURING MAGNETIC VARIABLES</topic><topic>PHYSICS</topic><topic>TESTING</topic><toplevel>online_resources</toplevel><creatorcontrib>HIKICHI HIROSHI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>HIKICHI HIROSHI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>VIRTUAL TEST SYSTEM CORRESPONDING TO SIMULTANEOUS TEST OF A PLURALITY OF DEVICE UNDER-TESTS (DUT)</title><date>2010-09-09</date><risdate>2010</risdate><abstract>PROBLEM TO BE SOLVED: To sufficiently debug an accurate test program. SOLUTION: A virtual test system includes: a plurality of semiconductor operation simulation models 201-1 to 201-32 provided corresponding to a plurality of the device under-tests (DUT); an operation simulation model 101 of an LSI tester for simultaneously testing the plurality of DUTs; and signal delay models 301-1 to 301-32 on a test board mounting the plurality of DUTs. The virtual test system adds the signal delay models 301-1 to 301-32 corresponding to signal lines on the test board to the signal lines connecting the plurality of the semiconductor operation simulation models 201-1 to 201-32 and the operation simulation model 101 of the LSI tester. COPYRIGHT: (C)2010,JPO&INPIT</abstract><oa>free_for_read</oa></addata></record>
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subjects	MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS TESTING
title	VIRTUAL TEST SYSTEM CORRESPONDING TO SIMULTANEOUS TEST OF A PLURALITY OF DEVICE UNDER-TESTS (DUT)
url	https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-03T17%3A16%3A55IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=HIKICHI%20HIROSHI&rft.date=2010-09-09&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EJP2010197356A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true