SEMICONDUCTOR INTEGRATED CIRCUIT, TESTING METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT, AND SEMICONDUCTOR INTEGRATED CIRCUIT PACKAGE

SEMICONDUCTOR INTEGRATED CIRCUIT, TESTING METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT, AND SEMICONDUCTOR INTEGRATED CIRCUIT PACKAGE

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit in which generation of leakage current is prevented while making available a pad of an IO block selected from at least two selection IO blocks, and to provide a testing method of the semiconductor integrated circuit, and semiconduct...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: HASUMI YUICHI, UCHIDA NOBUO, TAGUCHI OSAMU
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
BASIC ELECTRONIC CIRCUITRY
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
MEASURING
MEASURING ELECTRIC VARIABLES
MEASURING MAGNETIC VARIABLES
PHYSICS
PULSE TECHNIQUE
SEMICONDUCTOR DEVICES
TESTING
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit in which generation of leakage current is prevented while making available a pad of an IO block selected from at least two selection IO blocks, and to provide a testing method of the semiconductor integrated circuit, and semiconductor integrated circuit package in which the semiconductor integrated circuit is mounted. SOLUTION: A signal input to a pad 101 connected to a first dedicated IO buffer 110 which is brought into an input mode, is output from a tertiary input buffer included in the first dedicated IO buffer to a common signal line 13, this signal is supplied through a tertiary output buffer included in a second dedicated IO buffer 210 brought into an output mode, to a tertiary input buffer included in the second dedicated IO buffer 210, and its input voltage is determined. COPYRIGHT: (C)2010,JPO&INPIT