METHOD FOR PRODUCING INTERCONNECT STRUCTURES FOR INTEGRATED CIRCUITS

PROBLEM TO BE SOLVED: To provide a method for producing a semiconductor device which removes the overburden of barrier and conductive material using chemical mechanical polishing (CMP), thereby creating a larger process window to compensate for non-uniformity in deposition. SOLUTION: The method for...

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Bibliographische Detailangaben
Hauptverfasser: VAES JAN, HUYGHEBAERT CEDRIC, VAN OLMEN JAN
Format: Patent
Sprache:eng
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Zusammenfassung:PROBLEM TO BE SOLVED: To provide a method for producing a semiconductor device which removes the overburden of barrier and conductive material using chemical mechanical polishing (CMP), thereby creating a larger process window to compensate for non-uniformity in deposition. SOLUTION: The method for producing the semiconductor device includes the steps of: depositing a top layer 2 of dielectric material on the surface of a substrate 1; etching a first opening 7, filling the first opening using a first conductive material 8, and performing a first CMP step to form a first conductive structure 3; etching one second opening 13, filling the second opening using a second conductive material 10, and performing a second CMP step to form a second conductive structure 4. The method also includes the step of depositing a common CMP stopping layer 5 on the dielectric top layer, before the step of etching the first opening for filling, so that the CMP stopping layer is used for stopping the CMP process after filling of the first opening as well as the CMP process after filling of the second opening. COPYRIGHT: (C)2010,JPO&INPIT