CLOCK CONTROL CIRCUIT

PROBLEM TO BE SOLVED: To obtain a clock control circuit easy in circuit design which can suspend an output of a clock signal without causing a glitch and the corruption of a duty in the clock signal when the output suspension of the clock signal is instructed. SOLUTION: In a shift register 32 which operates in synchronization with a reference clock signal CLK480, after 8 periods of the signal CLK480 while a suspend signal SUSPENDM is changed from 1 to 0, the output SUSPR[0]-[7] of each flip-flop 34-48 is changed from 1 to 0, the output SUSR from an OR circuit 50 is changed from 1 to 0. A comparator 54 compares 3 bits data CLKREG[2:0] outputted from a register 28 with a fixed value, an output CGEN becomes zero during the CLKREG is equal to or lower than the fixed value. When the SUSR and the CGEN become 0, respectively, the output SUSI of an OR circuit 52 and the output SUSP of a flip-flop 56 become 0, thereby the data CLKREG are reset to be 0, and the output of the clock signal CLK is suspended. COPYRIGHT: (C)2010,JPO&INPIT