METHOD AND SYSTEM FOR DESIGN RULE CHECKING ENHANCED WITH PATTERN MATCHING

PROBLEM TO BE SOLVED: To enable circuit designers to waive certain design rules for their circuit designs. SOLUTION: One embodiment of the invention includes receiving a first layout pattern containing a new layout of an integrated circuit pattern, a pattern matcher 110 processes the layout pattern...

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Bibliographische Detailangaben
Hauptverfasser:	LAI YAIEH, GENNARI FRANK, MOSKEWICZ MATTHEW
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS CALCULATING CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ELECTRICITY MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS PHYSICS PRINTED CIRCUITS SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:	PROBLEM TO BE SOLVED: To enable circuit designers to waive certain design rules for their circuit designs. SOLUTION: One embodiment of the invention includes receiving a first layout pattern containing a new layout of an integrated circuit pattern, a pattern matcher 110 processes the layout pattern and designates certain patterns of the integrated circuit pattern that meet design waiver information. The pattern matcher 110 generates a second layout pattern with the waived patterns marked. A design rule checker 115 subsequently processes the marked layout pattern and validates all but the marked patterns of the second layout pattern against a set of specified design rules. The design rule checker 115 generates a third layout pattern with only the unmarked patterns of the layout being validated against the set of specified design rules. COPYRIGHT: (C)2010,JPO&INPIT