BIAS VOLTAGE GENERATION CIRCUIT AND DRIVER INTEGRATED CIRCUIT

PROBLEM TO BE SOLVED: To easily generate a corrected variable bias voltage by a comparatively simple circuit configuration. SOLUTION: A bias voltage generation circuit 50 comprises: a register 51 which holds a variable n-bit register value RV set externally; a nonvolatile memory 52 for storing n-bit...

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1. Verfasser:	TOMITA SHUNICHI
Format:	Patent
Sprache:	eng
Schlagworte:	ADVERTISING ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICESUSING STATIC MEANS TO PRESENT VARIABLE INFORMATION BASIC ELECTRIC ELEMENTS CONTROLLING CRYPTOGRAPHY DEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH ISMODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THEDEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY,COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g.SWITCHING, GATING, MODULATING OR DEMODULATING DISPLAY EDUCATION ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY FREQUENCY-CHANGING NON-LINEAR OPTICS OPTICAL ANALOGUE/DIGITAL CONVERTERS OPTICAL LOGIC ELEMENTS OPTICS PHYSICS REGULATING SEALS SEMICONDUCTOR DEVICES SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF
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Beschreibung
Zusammenfassung:	PROBLEM TO BE SOLVED: To easily generate a corrected variable bias voltage by a comparatively simple circuit configuration. SOLUTION: A bias voltage generation circuit 50 comprises: a register 51 which holds a variable n-bit register value RV set externally; a nonvolatile memory 52 for storing n-bit correction values CV0 to CV7 for correcting the data value RV; A computing circuit 60 which computes the n-bit register value RV and the n-bit correction values CV0 to CV7 and outputs n-bit arithmetic operation results S0 to S7; a resistance voltage division circuit 70 divides reference voltage VRS into 2nvoltages and outputs 2nlevels of divided voltages; and a selection circuit 80 which selects one level of a divided voltage DV from the 2nlevels of divided voltages DV0 to DV255 respectively on the basis of the n-bit computing results S0 to S7, and outputs a bias voltage BV having a variation over 2nlevels. COPYRIGHT: (C)2010,JPO&INPIT