SEMICONDUCTOR DEVICE

PROBLEM TO BE SOLVED: To improve heat dissipation performance, reliability and reduction in manufacturing cost in a semiconductor device. SOLUTION: In a BGA (ball grid array) 8 in which an SOC (system on chip) 1 is mounted on a wiring board 3, the SOC 1 includes an operation circuit 1g having at lea...

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Hauptverfasser: NAKAI TATSUO, SATO SUMIYOSHI, YAMADA YUICHIRO
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creator NAKAI TATSUO
SATO SUMIYOSHI
YAMADA YUICHIRO
description PROBLEM TO BE SOLVED: To improve heat dissipation performance, reliability and reduction in manufacturing cost in a semiconductor device. SOLUTION: In a BGA (ball grid array) 8 in which an SOC (system on chip) 1 is mounted on a wiring board 3, the SOC 1 includes an operation circuit 1g having at least one part of a region on the center portion of the SOC 1, a second pad 1i is provided on the operation circuit 1g of the main surface of the SOC 1, and the second pad 1i is directly connected to a bonding lead 3c of the wiring board 3 by a second wire 4b. With this configuration, the heat generated from the operation circuit 1g is dissipated to the wiring board 3 through the second wire 4b, and the heat dissipation performance of the BGA 8 is improved. COPYRIGHT: (C)2010,JPO&INPIT
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JP2010034101A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JP2010034101A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JP2010034101A3</originalsourceid><addsrcrecordid>eNrjZBAJdvX1dPb3cwl1DvEPUnBxDfN0duVhYE1LzClO5YXS3AxKbq4hzh66qQX58anFBYnJqXmpJfFeAUYGhgYGxiaGBoaOxkQpAgC5qB72</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>SEMICONDUCTOR DEVICE</title><source>esp@cenet</source><creator>NAKAI TATSUO ; SATO SUMIYOSHI ; YAMADA YUICHIRO</creator><creatorcontrib>NAKAI TATSUO ; SATO SUMIYOSHI ; YAMADA YUICHIRO</creatorcontrib><description>PROBLEM TO BE SOLVED: To improve heat dissipation performance, reliability and reduction in manufacturing cost in a semiconductor device. SOLUTION: In a BGA (ball grid array) 8 in which an SOC (system on chip) 1 is mounted on a wiring board 3, the SOC 1 includes an operation circuit 1g having at least one part of a region on the center portion of the SOC 1, a second pad 1i is provided on the operation circuit 1g of the main surface of the SOC 1, and the second pad 1i is directly connected to a bonding lead 3c of the wiring board 3 by a second wire 4b. With this configuration, the heat generated from the operation circuit 1g is dissipated to the wiring board 3 through the second wire 4b, and the heat dissipation performance of the BGA 8 is improved. COPYRIGHT: (C)2010,JPO&amp;INPIT</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2010</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20100212&amp;DB=EPODOC&amp;CC=JP&amp;NR=2010034101A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20100212&amp;DB=EPODOC&amp;CC=JP&amp;NR=2010034101A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>NAKAI TATSUO</creatorcontrib><creatorcontrib>SATO SUMIYOSHI</creatorcontrib><creatorcontrib>YAMADA YUICHIRO</creatorcontrib><title>SEMICONDUCTOR DEVICE</title><description>PROBLEM TO BE SOLVED: To improve heat dissipation performance, reliability and reduction in manufacturing cost in a semiconductor device. SOLUTION: In a BGA (ball grid array) 8 in which an SOC (system on chip) 1 is mounted on a wiring board 3, the SOC 1 includes an operation circuit 1g having at least one part of a region on the center portion of the SOC 1, a second pad 1i is provided on the operation circuit 1g of the main surface of the SOC 1, and the second pad 1i is directly connected to a bonding lead 3c of the wiring board 3 by a second wire 4b. With this configuration, the heat generated from the operation circuit 1g is dissipated to the wiring board 3 through the second wire 4b, and the heat dissipation performance of the BGA 8 is improved. COPYRIGHT: (C)2010,JPO&amp;INPIT</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2010</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZBAJdvX1dPb3cwl1DvEPUnBxDfN0duVhYE1LzClO5YXS3AxKbq4hzh66qQX58anFBYnJqXmpJfFeAUYGhgYGxiaGBoaOxkQpAgC5qB72</recordid><startdate>20100212</startdate><enddate>20100212</enddate><creator>NAKAI TATSUO</creator><creator>SATO SUMIYOSHI</creator><creator>YAMADA YUICHIRO</creator><scope>EVB</scope></search><sort><creationdate>20100212</creationdate><title>SEMICONDUCTOR DEVICE</title><author>NAKAI TATSUO ; SATO SUMIYOSHI ; YAMADA YUICHIRO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2010034101A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2010</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>NAKAI TATSUO</creatorcontrib><creatorcontrib>SATO SUMIYOSHI</creatorcontrib><creatorcontrib>YAMADA YUICHIRO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>NAKAI TATSUO</au><au>SATO SUMIYOSHI</au><au>YAMADA YUICHIRO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SEMICONDUCTOR DEVICE</title><date>2010-02-12</date><risdate>2010</risdate><abstract>PROBLEM TO BE SOLVED: To improve heat dissipation performance, reliability and reduction in manufacturing cost in a semiconductor device. SOLUTION: In a BGA (ball grid array) 8 in which an SOC (system on chip) 1 is mounted on a wiring board 3, the SOC 1 includes an operation circuit 1g having at least one part of a region on the center portion of the SOC 1, a second pad 1i is provided on the operation circuit 1g of the main surface of the SOC 1, and the second pad 1i is directly connected to a bonding lead 3c of the wiring board 3 by a second wire 4b. With this configuration, the heat generated from the operation circuit 1g is dissipated to the wiring board 3 through the second wire 4b, and the heat dissipation performance of the BGA 8 is improved. COPYRIGHT: (C)2010,JPO&amp;INPIT</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title SEMICONDUCTOR DEVICE
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-01T00%3A35%3A11IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=NAKAI%20TATSUO&rft.date=2010-02-12&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EJP2010034101A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true