LEVEL UP CONVERSION CIRCUIT
PROBLEM TO BE SOLVED: To provide a level up conversion circuit that achieves high reliability, by reducing variation in delay time caused by variation in a high voltage side power supply voltage, and by reducing clock jitter in use for clock output, and that is also available for a high-speed signal...
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| Format: | Patent |
| Sprache: | eng |
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| Zusammenfassung: | PROBLEM TO BE SOLVED: To provide a level up conversion circuit that achieves high reliability, by reducing variation in delay time caused by variation in a high voltage side power supply voltage, and by reducing clock jitter in use for clock output, and that is also available for a high-speed signal line where the high voltage side power supply voltage is decreased. SOLUTION: PMOS transistors PM7, PM8 are provided and when an input digital signal SIN is VDDL (H level), a potential of a node N5 is set to a high voltage side power supply voltage VDDH. When the input digital signal SIN is changed into 0V (L level), the time for turning the PMOS transistor PM2 from OFF to ON is shortened. COPYRIGHT: (C)2010,JPO&INPIT |
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