TRANSISTOR WITH ULTRA-SHORT GATE SHAPE AND MEMORY CELL, AND METHOD OF MANUFACTURING THEM
PROBLEM TO BE SOLVED: To provide a semiconductor element allowing channel length to be dramatically scaled by manufacturing a high-performance transistor and a memory cell exhibiting strong program/erasure efficiency and reading speed, and having a very small gate shape and a total size allowing a l...
Gespeichert in:
Hauptverfasser: | , , |
---|---|
Format: | Patent |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
Zusammenfassung: | PROBLEM TO BE SOLVED: To provide a semiconductor element allowing channel length to be dramatically scaled by manufacturing a high-performance transistor and a memory cell exhibiting strong program/erasure efficiency and reading speed, and having a very small gate shape and a total size allowing a low operation voltage; and a manufacturing method thereof. SOLUTION: The method of forming a semiconductor transistor includes processes of: forming a gate electrode over but insulated from a semiconductor substrate region 100; forming off-set spacers 110a, 110b along side-walls of the gate electrode; and forming a source region and a drain region in the substrate region after forming the off-set spacers so that the extent of an overlap between the gate electrode and each of the source and drain regions is dependent on the thickness of the off-set spacers. COPYRIGHT: (C)2010,JPO&INPIT |
---|