METHOD FOR MANUFACTURING SOLDER BUMP

PROBLEM TO BE SOLVED: To provide a method for manufacturing solder bumps, which can improve the accuracy in the weight ratio of Sn to Cu. SOLUTION: A resist layer 40 having an aperture 41 is formed on a UBM layer 30 formed on a semiconductor element 20, and a Cu plating layer 11 of which the thickne...

Ausführliche Beschreibung

Gespeichert in:

Bibliographische Detailangaben
Hauptverfasser:	KATO KYOKO, TOGASAKI TAKASHI
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!

Beschreibung
Zusammenfassung:	PROBLEM TO BE SOLVED: To provide a method for manufacturing solder bumps, which can improve the accuracy in the weight ratio of Sn to Cu. SOLUTION: A resist layer 40 having an aperture 41 is formed on a UBM layer 30 formed on a semiconductor element 20, and a Cu plating layer 11 of which the thickness is substantially 0 is formed on the inner surface of the aperture 41 by an electric plating method; and after further forming an Sn plating layer 12 in the aperture 41, the resist layer 40 is removed, the UBM layer 30 is etched, and the Cu plating layer 11 and the Sn plating layer 12 are reflowed to form a solder bump of Sn-0.7Cu. COPYRIGHT: (C)2010,JPO&INPIT