SEMICONDUCTOR DEVICE

PROBLEM TO BE SOLVED: To provide a semiconductor device wherein the resistance delay in a selective gate region and a peripheral circuit region is avoided while miniaturizing a memory cell array region. SOLUTION: The semiconductor device includes: a first insulating film 12 formed on a semiconductor layer; a first electrode layer 13; a plurality of element isolation regions 15 which are formed to extend up to the inside of the semiconductor layer through the first electrode layer 13 and the first insulating film 12 and are self-aligned with the first electrode layer 13 and separate element regions and comprise an element isolating insulating film; a second insulating film 16 which is formed on the first electrode layer 13 across the element isolation regions 15 and includes an open portion through which a surface of the first electrode layer 13 is exposed; a second electrode layer 18 which is formed on the second insulating film 16 and the exposed surface of the first electrode layer 13 and is electrically connected to the first electrode layer 13 via the open portion and includes a lower resistance than the first electrode layer 13; and a contact hole 20 and upper layer wiring 21 which are located above the element isolation regions 15 and are electrically connected to the second electrode layer 18. COPYRIGHT: (C)2010,JPO&INPIT