RECTIFIER ELEMENT

PROBLEM TO BE SOLVED: To provide a manufacturing method for improving an integration degree of a semiconductor rectifier element and reducing loss by reducing voltage drop in the forward direction. SOLUTION: An n type single-crystal silicon layer 12 is formed, and a groove 13 is provided on a first...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: MASASHIRO TAKAHISA, MATSUMOTO SATOSHI
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator MASASHIRO TAKAHISA
MATSUMOTO SATOSHI
description PROBLEM TO BE SOLVED: To provide a manufacturing method for improving an integration degree of a semiconductor rectifier element and reducing loss by reducing voltage drop in the forward direction. SOLUTION: An n type single-crystal silicon layer 12 is formed, and a groove 13 is provided on a first principal plane of a high concentration n type single-crystal silicon substrate 11. A titanium layer 14 is formed in the groove 13, a groove 15 is provided in a partial region of the bottom of the groove 13, and an insulating film 16 is formed in the groove 15. A p type polysilicon embedded layer 17 is formed in the insulating film. A high concentration n type single-crystal silicon layer 18 from the first principal plane of the semiconductor layer 12 to the semiconductor substrate 11 is formed. A groove 19 is provided in the semiconductor layer 12 between the groove 13 and the high concentration semiconductor layer 18, and an insulating film 20 is formed in the groove 19. A p type polysilicon embedded layer 21 is formed in the insulating film 20. An insulating film 22 is formed on the first principal plane of the semiconductor layer 12, and the metal layer 14 is connected to the embedded conductor layer 21. COPYRIGHT: (C)2010,JPO&INPIT
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JP2009253122A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JP2009253122A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JP2009253122A3</originalsourceid><addsrcrecordid>eNrjZBAMcnUO8XTzdA1ScPVx9XX1C-FhYE1LzClO5YXS3AxKbq4hzh66qQX58anFBYnJqXmpJfFeAUYGBpZGpsaGRkaOxkQpAgBXlB4n</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>RECTIFIER ELEMENT</title><source>esp@cenet</source><creator>MASASHIRO TAKAHISA ; MATSUMOTO SATOSHI</creator><creatorcontrib>MASASHIRO TAKAHISA ; MATSUMOTO SATOSHI</creatorcontrib><description>PROBLEM TO BE SOLVED: To provide a manufacturing method for improving an integration degree of a semiconductor rectifier element and reducing loss by reducing voltage drop in the forward direction. SOLUTION: An n type single-crystal silicon layer 12 is formed, and a groove 13 is provided on a first principal plane of a high concentration n type single-crystal silicon substrate 11. A titanium layer 14 is formed in the groove 13, a groove 15 is provided in a partial region of the bottom of the groove 13, and an insulating film 16 is formed in the groove 15. A p type polysilicon embedded layer 17 is formed in the insulating film. A high concentration n type single-crystal silicon layer 18 from the first principal plane of the semiconductor layer 12 to the semiconductor substrate 11 is formed. A groove 19 is provided in the semiconductor layer 12 between the groove 13 and the high concentration semiconductor layer 18, and an insulating film 20 is formed in the groove 19. A p type polysilicon embedded layer 21 is formed in the insulating film 20. An insulating film 22 is formed on the first principal plane of the semiconductor layer 12, and the metal layer 14 is connected to the embedded conductor layer 21. COPYRIGHT: (C)2010,JPO&amp;INPIT</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2009</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20091029&amp;DB=EPODOC&amp;CC=JP&amp;NR=2009253122A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76516</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20091029&amp;DB=EPODOC&amp;CC=JP&amp;NR=2009253122A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>MASASHIRO TAKAHISA</creatorcontrib><creatorcontrib>MATSUMOTO SATOSHI</creatorcontrib><title>RECTIFIER ELEMENT</title><description>PROBLEM TO BE SOLVED: To provide a manufacturing method for improving an integration degree of a semiconductor rectifier element and reducing loss by reducing voltage drop in the forward direction. SOLUTION: An n type single-crystal silicon layer 12 is formed, and a groove 13 is provided on a first principal plane of a high concentration n type single-crystal silicon substrate 11. A titanium layer 14 is formed in the groove 13, a groove 15 is provided in a partial region of the bottom of the groove 13, and an insulating film 16 is formed in the groove 15. A p type polysilicon embedded layer 17 is formed in the insulating film. A high concentration n type single-crystal silicon layer 18 from the first principal plane of the semiconductor layer 12 to the semiconductor substrate 11 is formed. A groove 19 is provided in the semiconductor layer 12 between the groove 13 and the high concentration semiconductor layer 18, and an insulating film 20 is formed in the groove 19. A p type polysilicon embedded layer 21 is formed in the insulating film 20. An insulating film 22 is formed on the first principal plane of the semiconductor layer 12, and the metal layer 14 is connected to the embedded conductor layer 21. COPYRIGHT: (C)2010,JPO&amp;INPIT</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2009</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZBAMcnUO8XTzdA1ScPVx9XX1C-FhYE1LzClO5YXS3AxKbq4hzh66qQX58anFBYnJqXmpJfFeAUYGBpZGpsaGRkaOxkQpAgBXlB4n</recordid><startdate>20091029</startdate><enddate>20091029</enddate><creator>MASASHIRO TAKAHISA</creator><creator>MATSUMOTO SATOSHI</creator><scope>EVB</scope></search><sort><creationdate>20091029</creationdate><title>RECTIFIER ELEMENT</title><author>MASASHIRO TAKAHISA ; MATSUMOTO SATOSHI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2009253122A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2009</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>MASASHIRO TAKAHISA</creatorcontrib><creatorcontrib>MATSUMOTO SATOSHI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>MASASHIRO TAKAHISA</au><au>MATSUMOTO SATOSHI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>RECTIFIER ELEMENT</title><date>2009-10-29</date><risdate>2009</risdate><abstract>PROBLEM TO BE SOLVED: To provide a manufacturing method for improving an integration degree of a semiconductor rectifier element and reducing loss by reducing voltage drop in the forward direction. SOLUTION: An n type single-crystal silicon layer 12 is formed, and a groove 13 is provided on a first principal plane of a high concentration n type single-crystal silicon substrate 11. A titanium layer 14 is formed in the groove 13, a groove 15 is provided in a partial region of the bottom of the groove 13, and an insulating film 16 is formed in the groove 15. A p type polysilicon embedded layer 17 is formed in the insulating film. A high concentration n type single-crystal silicon layer 18 from the first principal plane of the semiconductor layer 12 to the semiconductor substrate 11 is formed. A groove 19 is provided in the semiconductor layer 12 between the groove 13 and the high concentration semiconductor layer 18, and an insulating film 20 is formed in the groove 19. A p type polysilicon embedded layer 21 is formed in the insulating film 20. An insulating film 22 is formed on the first principal plane of the semiconductor layer 12, and the metal layer 14 is connected to the embedded conductor layer 21. COPYRIGHT: (C)2010,JPO&amp;INPIT</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_JP2009253122A
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title RECTIFIER ELEMENT
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-15T09%3A42%3A42IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=MASASHIRO%20TAKAHISA&rft.date=2009-10-29&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EJP2009253122A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true