PROGRAM FOR SUPPORTING TEST-FACILITATING DESIGN OF SEMICONDUCTOR INTEGRATED CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT

PROBLEM TO BE SOLVED: To reduce the TAT (Turn Around Time) required to meet the timing requirements of clock pulse propagation in the normal operating mode and the test operating mode of an integrated circuit. SOLUTION: A program (Figure 3) for supporting the DFT (Design For Test) of the semiconductor integrated circuit includes: a step (S202) for inputting a first net list steps (S204, S206) for determining the position (234) of a clock route (402) and generating clock tree information (236) such that logic elements on a clock signal path are expressed in tree form; a step (S208) for generating, out of the tree information, terminal position information (238) indicating the terminals of controlled logic elements (408, 412, 418) for testing; a step (S210) for generating integrated position information (242) indicating the integrated position of a controllable logic element for testing for the controlled logic elements; and a step (S212) for generating a second net list such that controlling logic elements (403, 407, 413, 417) for testing are integrated into the first net list. COPYRIGHT: (C)2009,JPO&INPIT