CONNECTOR PACKAGING SUBSTRATE AND METHOD OF TESTING CONNECTOR PACKAGING SUBSTRATE

PROBLEM TO BE SOLVED: To provide a packaging substrate that can prevent the connection error occurring when external connector is connected to a connector disposed in a printed circuit board. SOLUTION: A connector packaging substrate includes: a printed circuit board 2; a connector 5 connected to wi...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: TONO YASUTAKA, MORITA KENTA, HIKIMA KATSUAKI, SATO AKIHIRO, NAKANO TAKESHI
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator TONO YASUTAKA
MORITA KENTA
HIKIMA KATSUAKI
SATO AKIHIRO
NAKANO TAKESHI
description PROBLEM TO BE SOLVED: To provide a packaging substrate that can prevent the connection error occurring when external connector is connected to a connector disposed in a printed circuit board. SOLUTION: A connector packaging substrate includes: a printed circuit board 2; a connector 5 connected to wiring the printed circuit board 2; and a plurality of substrate connector 3 formed on the surface 4a of the printed circuit board 2, each having a body 6 holding the terminal 5. The colors of the bodies 6 of the plurality of the substrate connector 3 are different each other. Respective bodies 6 are formed almost the same shape and size with insert hole 11 for inserting external connector. The inner circumference 16 of the body 6 facing to the insert hole 11 has a barrier 17 for preventing to move the external connector to be inserted to another body 6 for inserting direction. COPYRIGHT: (C)2009,JPO&INPIT
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JP2009188358A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JP2009188358A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JP2009188358A3</originalsourceid><addsrcrecordid>eNrjZAh09vfzc3UO8Q9SCHB09nZ09_RzVwgOdQoOCXIMcVVw9HNR8HUN8fB3UfB3UwhxDQ4ByePVw8PAmpaYU5zKC6W5GZTcXEOcPXRTC_LjU4sLEpNT81JL4r0CjAwMLA0tLIxNLRyNiVIEABSUMAU</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>CONNECTOR PACKAGING SUBSTRATE AND METHOD OF TESTING CONNECTOR PACKAGING SUBSTRATE</title><source>esp@cenet</source><creator>TONO YASUTAKA ; MORITA KENTA ; HIKIMA KATSUAKI ; SATO AKIHIRO ; NAKANO TAKESHI</creator><creatorcontrib>TONO YASUTAKA ; MORITA KENTA ; HIKIMA KATSUAKI ; SATO AKIHIRO ; NAKANO TAKESHI</creatorcontrib><description>PROBLEM TO BE SOLVED: To provide a packaging substrate that can prevent the connection error occurring when external connector is connected to a connector disposed in a printed circuit board. SOLUTION: A connector packaging substrate includes: a printed circuit board 2; a connector 5 connected to wiring the printed circuit board 2; and a plurality of substrate connector 3 formed on the surface 4a of the printed circuit board 2, each having a body 6 holding the terminal 5. The colors of the bodies 6 of the plurality of the substrate connector 3 are different each other. Respective bodies 6 are formed almost the same shape and size with insert hole 11 for inserting external connector. The inner circumference 16 of the body 6 facing to the insert hole 11 has a barrier 17 for preventing to move the external connector to be inserted to another body 6 for inserting direction. COPYRIGHT: (C)2009,JPO&amp;INPIT</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ; CURRENT COLLECTORS ; ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; LINE CONNECTORS ; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ; PRINTED CIRCUITS</subject><creationdate>2009</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20090820&amp;DB=EPODOC&amp;CC=JP&amp;NR=2009188358A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,778,883,25551,76302</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20090820&amp;DB=EPODOC&amp;CC=JP&amp;NR=2009188358A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>TONO YASUTAKA</creatorcontrib><creatorcontrib>MORITA KENTA</creatorcontrib><creatorcontrib>HIKIMA KATSUAKI</creatorcontrib><creatorcontrib>SATO AKIHIRO</creatorcontrib><creatorcontrib>NAKANO TAKESHI</creatorcontrib><title>CONNECTOR PACKAGING SUBSTRATE AND METHOD OF TESTING CONNECTOR PACKAGING SUBSTRATE</title><description>PROBLEM TO BE SOLVED: To provide a packaging substrate that can prevent the connection error occurring when external connector is connected to a connector disposed in a printed circuit board. SOLUTION: A connector packaging substrate includes: a printed circuit board 2; a connector 5 connected to wiring the printed circuit board 2; and a plurality of substrate connector 3 formed on the surface 4a of the printed circuit board 2, each having a body 6 holding the terminal 5. The colors of the bodies 6 of the plurality of the substrate connector 3 are different each other. Respective bodies 6 are formed almost the same shape and size with insert hole 11 for inserting external connector. The inner circumference 16 of the body 6 facing to the insert hole 11 has a barrier 17 for preventing to move the external connector to be inserted to another body 6 for inserting direction. COPYRIGHT: (C)2009,JPO&amp;INPIT</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</subject><subject>CURRENT COLLECTORS</subject><subject>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>LINE CONNECTORS</subject><subject>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</subject><subject>PRINTED CIRCUITS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2009</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZAh09vfzc3UO8Q9SCHB09nZ09_RzVwgOdQoOCXIMcVVw9HNR8HUN8fB3UfB3UwhxDQ4ByePVw8PAmpaYU5zKC6W5GZTcXEOcPXRTC_LjU4sLEpNT81JL4r0CjAwMLA0tLIxNLRyNiVIEABSUMAU</recordid><startdate>20090820</startdate><enddate>20090820</enddate><creator>TONO YASUTAKA</creator><creator>MORITA KENTA</creator><creator>HIKIMA KATSUAKI</creator><creator>SATO AKIHIRO</creator><creator>NAKANO TAKESHI</creator><scope>EVB</scope></search><sort><creationdate>20090820</creationdate><title>CONNECTOR PACKAGING SUBSTRATE AND METHOD OF TESTING CONNECTOR PACKAGING SUBSTRATE</title><author>TONO YASUTAKA ; MORITA KENTA ; HIKIMA KATSUAKI ; SATO AKIHIRO ; NAKANO TAKESHI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2009188358A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2009</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</topic><topic>CURRENT COLLECTORS</topic><topic>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>LINE CONNECTORS</topic><topic>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</topic><topic>PRINTED CIRCUITS</topic><toplevel>online_resources</toplevel><creatorcontrib>TONO YASUTAKA</creatorcontrib><creatorcontrib>MORITA KENTA</creatorcontrib><creatorcontrib>HIKIMA KATSUAKI</creatorcontrib><creatorcontrib>SATO AKIHIRO</creatorcontrib><creatorcontrib>NAKANO TAKESHI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>TONO YASUTAKA</au><au>MORITA KENTA</au><au>HIKIMA KATSUAKI</au><au>SATO AKIHIRO</au><au>NAKANO TAKESHI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>CONNECTOR PACKAGING SUBSTRATE AND METHOD OF TESTING CONNECTOR PACKAGING SUBSTRATE</title><date>2009-08-20</date><risdate>2009</risdate><abstract>PROBLEM TO BE SOLVED: To provide a packaging substrate that can prevent the connection error occurring when external connector is connected to a connector disposed in a printed circuit board. SOLUTION: A connector packaging substrate includes: a printed circuit board 2; a connector 5 connected to wiring the printed circuit board 2; and a plurality of substrate connector 3 formed on the surface 4a of the printed circuit board 2, each having a body 6 holding the terminal 5. The colors of the bodies 6 of the plurality of the substrate connector 3 are different each other. Respective bodies 6 are formed almost the same shape and size with insert hole 11 for inserting external connector. The inner circumference 16 of the body 6 facing to the insert hole 11 has a barrier 17 for preventing to move the external connector to be inserted to another body 6 for inserting direction. COPYRIGHT: (C)2009,JPO&amp;INPIT</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_JP2009188358A
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS
CURRENT COLLECTORS
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
LINE CONNECTORS
MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
PRINTED CIRCUITS
title CONNECTOR PACKAGING SUBSTRATE AND METHOD OF TESTING CONNECTOR PACKAGING SUBSTRATE
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-16T04%3A59%3A10IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=TONO%20YASUTAKA&rft.date=2009-08-20&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EJP2009188358A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true