DATA PROCESSOR AND METHOD FOR TESTING STABILITY OF MEMORY CELL IN MEMORY DEVICE

PROBLEM TO BE SOLVED: To provide a data processor and method for testing stability of a cell using a reliable, effective and practical (in connection with test time period) mechanism for detecting a defective memory cell that may malfunction in normal use due to unstableness of the cell caused by a hysteresis effect in a body region of transistors configuring the memory cell in a memory device. SOLUTION: The defective memory cell is detected by continuing dummy read operation on the same memory cell immediately after write operation on the memory cell with an internal clock signal having a frequency increased with respect to a test mode clock signal responsive to each write access request issued according to a test pattern, and surely simulating the worst case. COPYRIGHT: (C)2009,JPO&INPIT