CACHE MEMORY SYSTEM, AND CACHE MEMORY CONTROL METHOD

PROBLEM TO BE SOLVED: To provide a cache memory system preventing wasteful data transfer originating from a store instruction of a write allocation system. SOLUTION: When the store instruction is executed, the cache memory system executes selectively one of, a first operation mode of in response to...

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Bibliographische Detailangaben
Hauptverfasser: TAKEBE YOSHIMASA, TSUJI MASAYUKI, NOTOMI AKIRA
Format: Patent
Sprache:eng
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Zusammenfassung:PROBLEM TO BE SOLVED: To provide a cache memory system preventing wasteful data transfer originating from a store instruction of a write allocation system. SOLUTION: When the store instruction is executed, the cache memory system executes selectively one of, a first operation mode of in response to a generation of a cache miss due to an access to the address, copying data of the address of the main memory unit to the cache memory and then rewriting the copied data on the cache memory using the write data; and a second operation mode of allocating an area of the address to the cache memory in response to a generation of a cache, storing the write data in the allocated area on the cache memory without copying the data of the address of the main memory unit to the cache memory. COPYRIGHT: (C)2009,JPO&INPIT