HETERO-JUNCTION FIELD EFFECT TRANSISTOR AND METHOD OF PRODUCING THE SAME

PROBLEM TO BE SOLVED: To reduce a parasitic resistance in the lower side of source/drain electrodes by lowering potential barrier in the lower side of the source/drain electrodes. SOLUTION: The hetero-junction field effect transistor (FET) is formed of a nitride semiconductor and is provided with a...

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Hauptverfasser: OISHI TOSHIYUKI, TOKUDA YASUKI, FUKITA MUNEYOSHI, ABE YUJI, NANJO TAKUMA
Format: Patent
Sprache:eng
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Zusammenfassung:PROBLEM TO BE SOLVED: To reduce a parasitic resistance in the lower side of source/drain electrodes by lowering potential barrier in the lower side of the source/drain electrodes. SOLUTION: The hetero-junction field effect transistor (FET) is formed of a nitride semiconductor and is provided with a channel layer 30 and a barrier layer 50 formed on the channel layer 30 via a spacer layer 40. This transistor is further provided with a gate electrode 80 formed on the barrier layer 50 and source/drain electrodes 70 formed on the barrier layer 50 to hold the gate electrode 80. In addition, the transistor is also provided with at least a part of region in the lower side of the source/drain electrodes 70, for example, a type-n impurity region 90 formed on the barrier layer 50, spacer layer 40, and channel layer 30. COPYRIGHT: (C)2009,JPO&INPIT