HETERO-JUNCTION FIELD EFFECT TRANSISTOR AND METHOD OF PRODUCING THE SAME

PROBLEM TO BE SOLVED: To prevent increase in parasitic resistance by lowering potential barrier in the lower side of source/drain electrodes. SOLUTION: The hetero-junction field effect transistor (FET) is formed of a nitride semiconductor provided with including a channel layer 30 and a barrier laye...

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Bibliographische Detailangaben
Hauptverfasser: OISHI TOSHIYUKI, FUKITA MUNEYOSHI, ABE YUJI, NANJO TAKUMA
Format: Patent
Sprache:eng
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Zusammenfassung:PROBLEM TO BE SOLVED: To prevent increase in parasitic resistance by lowering potential barrier in the lower side of source/drain electrodes. SOLUTION: The hetero-junction field effect transistor (FET) is formed of a nitride semiconductor provided with including a channel layer 30 and a barrier layer 50 formed on the channel layer 30 via a spacer layer 40. Moreover, this transistor is additionally provided with a gate electrode 80 formed on the barrier layer 50 and source/drain electrodes 70 formed on the barrier layer 50 to hold the gate electrode 80. The spacer layer 40 is formed in a region at the lower side of the gate electrode 80 and is provided with a first spacer layer 41 that is larger in a band gap than any of the channel layer 30 and barrier layer 50. The spacer layer 40 is formed in a region at the lower side of the source/drain electrodes 70 and is provided with a second spacer layer 42 that is smaller in the band gap than the first spacer layer 41. COPYRIGHT: (C)2009,JPO&INPIT