ELEMENT ARRANGEMENT WIRING DEVICE, ELEMENT ARRANGEMENT WIRING METHOD, METHOD FOR MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT, CONTROL PROGRAM, AND READABLE STORAGE MEDIUM

PROBLEM TO BE SOLVED: To effectively reduce a delay by estimating the delay of a circuit by using a resistance value to determine an optimal buffer insertion position in reducing the delay due to buffer insertion of wiring because a correct resistance value of the wiring between circuit elements can be calculated by taking into consideration temperatures at respective positions of the wiring between the circuit elements constituting a semiconductor integrated circuit. SOLUTION: This element arrangement wiring device 100 is provided with a signal delay time deriving means 101 for deriving a signal delay time at a wiring, which corresponds to a temperature dependence resistance distribution depending upon a temperature distribution at the wiring from circuit information showing a basic layout of a semiconductor integrated circuit and heat distribution information showing a heat distribution in the semiconductor integrated circuit, and a position determining means 100a for determining a position for inserting a buffer gate so as to reduce a signal delay time at the wiring in the wiring on the basis of the temperature dependence resistance distribution at the wiring. COPYRIGHT: (C)2009,JPO&INPIT