MANUFACTURING METHOD OF SEMICONDUCTOR PACKAGE

PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor package, capable of achieving miniaturization and increasing the number of pins. SOLUTION: A wiring pattern 3 is formed on the front surface of a copper plate 1, external terminals 4 are formed on the rear surface and semicon...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
1. Verfasser: SAIGO YUKIO
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor package, capable of achieving miniaturization and increasing the number of pins. SOLUTION: A wiring pattern 3 is formed on the front surface of a copper plate 1, external terminals 4 are formed on the rear surface and semiconductor chips 5 are flip-chip bonded on the front surface of the copper plate. Subsequently, an underfill material 6 is injected into a gap between the copper plate and the semiconductor chips, the semiconductor chips are sealed with a molding resin and then the copper plate is etched to form a conductive path 8. After that, solder bumps 10 are formed after the conduction, and dicing processing is executed. COPYRIGHT: (C)2009,JPO&INPIT