BUS COMPARISON TYPE MULTIPLEX SYSTEM PROCESSOR

PROBLEM TO BE SOLVED: To provide a multiplex system processor having a bus comparison function as a means for achieving high security for always synchronizing each system CPU operation even if an interruption signal is input from the outside at arbitrary timing. SOLUTION: The processor is composed of two systems of CPUs 1, 2; a timing correction device 3; a bus synchronization device 4, a bus comparison device 5, and an input/output device 6. The same program operates on an (A) system CPU 1 and a (B) system CPU 2. The bus synchronization device 4 synchronizes for every access of each system CPU to a bus. The comparison device 5 compares bus signals such as addresses, data and control signals, and as a result if signals in the two systems do not coincide with one another, the comparison device 5 stops the input/output device 6 and transits a control object 7 into a secured state, and external interruption signals 8 accompanying the achievement of a function such as a communication and a timer are distributed to each system CPU through the correction device 3. COPYRIGHT: (C)2009,JPO&INPIT