INSPECTION SIGNAL GENERATING DEVICE AND SEMICONDUCTOR TEST DEVICE

PROBLEM TO BE SOLVED: To provide an inspection signal generating device and a semiconductor test device equipped with the inspection signal generating device concerned capable of reducing the time needed to inspection due to enhancement of the degree of freedom for address control. SOLUTION: The inspection signal generating device 1 includes a pattern memory 19 memorizing pattern data D10, a pattern address computing section 11 generating an address A11 using an address A22 designated before by the pattern memory 19 based on the pattern address control signal C10 input, address registers 12a to 12n memorizing address designating domains desired by the pattern memory 19, and an inspection signal generating section 20 generating inspection signal S10 based on the pattern data D10 read out from the pattern memory 19, by using either an address A11 generated by the pattern address computing section 11 or an address (address A30) memorized by the address registers 12a to 12n. COPYRIGHT: (C)2009,JPO&INPIT