SEMICONDUCTOR INTEGRATED CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT DESIGN SUPPORT DEVICE, AND METHOD FOR MANUFACTURING THE SEMICONDUCTOR INTEGRATED CIRCUIT

PROBLEM TO BE SOLVED: To manufacture a semiconductor integrated circuit capable of holding a failure detection ratio, even if a scanning ratio is decreased while reducing the increase in chip area, increase the power consumption, deterioration in timing convergence, and deterioration in wiring conve...

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Bibliographische Detailangaben
Hauptverfasser: SATOI TOMOKI, NISHIGAKI NAOHIKO
Format: Patent
Sprache:eng
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Zusammenfassung:PROBLEM TO BE SOLVED: To manufacture a semiconductor integrated circuit capable of holding a failure detection ratio, even if a scanning ratio is decreased while reducing the increase in chip area, increase the power consumption, deterioration in timing convergence, and deterioration in wiring convergence of layout. SOLUTION: The semiconductor integrated circuit including a user logic circuit is such that a circuit part that constitutes data shift comprises a register other than a scan cell, excluding a part immediately after a combination circuit, and a register constituent part other than the scan cell is utilized as a scan path. COPYRIGHT: (C)2008,JPO&INPIT