SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURING METHOD THEREOF

PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device having a configuration capable of relaxing a stress to be generated by mechanical dynamic stress caused by probing in inspection or wire bonding in assembly, and capable of dealing with screening such as low-temperature inspe...

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Bibliographische Detailangaben
Hauptverfasser: FUKAMIZU SHINGO, NABESHIMA TAMOTSU
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device having a configuration capable of relaxing a stress to be generated by mechanical dynamic stress caused by probing in inspection or wire bonding in assembly, and capable of dealing with screening such as low-temperature inspection, room-temperature inspection, high-temperature inspection in probe checking and wafer burn-in inspection or a plurality of times of probe checking in guarantee inspection which are becoming indispensable as wafer inspection dealing with large chip in micro-process. SOLUTION: The semiconductor integrated circuit device is provided with: an active element (100A); an interlayer insulating film; a first metal pattern and a second metal pattern formed immediately above the active element (100A) and made of a first metal layer; a first bus (140) and a second bus (150) formed immediately above the first metal layer and made of a second metal layer; and a contact pad (304) provided on the first bus (140) and the second bus (150). The contact pad (304) has a region (200a) for probe checking and a region (304a) for bonding. COPYRIGHT: (C)2008,JPO&INPIT