SEMICONDUCTOR DEVICE MANUFACTURING METHOD

PROBLEM TO BE SOLVED: To provide a means that reduces a variation range of a threshold voltage due to variations in film thickness of a silicon thin-film layer while reducing a leak current of a complete-depletion type semiconductor device formed onto a silicon thin-film layer on an insulating subst...

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1. Verfasser: FURUHIRA TAKAAKI
Format: Patent
Sprache:eng
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Zusammenfassung:PROBLEM TO BE SOLVED: To provide a means that reduces a variation range of a threshold voltage due to variations in film thickness of a silicon thin-film layer while reducing a leak current of a complete-depletion type semiconductor device formed onto a silicon thin-film layer on an insulating substrate. SOLUTION: A semiconductor device manufacturing method is used for manufacturing a complete-depletion type semiconductor device that is provided with a gate insulating film 11 formed on a silicon thin-film layer 2 formed on an insulating substrate 1, a gate electrode 12 formed on the gate insulating film, each high-concentration diffusion layer formed on each silicon thin-film layer on both sides of the gate electrode, and a channel region 10 formed in the silicon thin-film layer between the high-concentration diffusion layers. The method is provided with a first impurity implantation step, in which first impurities having the conduction type opposite to that of the high-concentration diffusion layer are implanted into the channel region so that a peak of an impurity concentration after implantation is located at a position shallower than a half of the film thickness of the silicon thin-film layer, and a second impurity implantation step for implanting second impurities having the conduction type opposite to that of the high-concentration diffusion layer into the channel region so that a peak of an impurity concentration after implantation is located at a position deeper than a half of the film thickness of the silicon thin-film layer. COPYRIGHT: (C)2008,JPO&INPIT