CAPACITOR-CONTAINING CHIP CARRIER SUBSTRATE AND ITS MANUFACTURING METHOD
PROBLEM TO BE SOLVED: To provide a chip carrier substrate comprising a capacitor aperture and a laterally separated via an aperture each of which is located in a substrate. SOLUTION: The capacitor aperture has a narrower line width and a shallower depth than those of the via aperture to obtain a mic...
Gespeichert in:
| Hauptverfasser: | , |
|---|---|
| Format: | Patent |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | PATEL CHIRAG SURYAKANT ANDRY PAUL STEPHEN |
| description | PROBLEM TO BE SOLVED: To provide a chip carrier substrate comprising a capacitor aperture and a laterally separated via an aperture each of which is located in a substrate. SOLUTION: The capacitor aperture has a narrower line width and a shallower depth than those of the via aperture to obtain a microloading effect in a plasma etching method that is used for simultaneously etching the capacitor aperture and the via aperture in the substrate. Subsequently a capacitor is formed and located in the capacitor aperture and a via is formed and located in the via apertures. Various combinations of a first capacitor plate layer, a capacitor dielectric layer and a second capacitor plate layer may be obtained continuously with respect to the capacitor aperture and the via aperture. COPYRIGHT: (C)2008,JPO&INPIT |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JP2008177576A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JP2008177576A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JP2008177576A3</originalsourceid><addsrcrecordid>eNqNyrEKwjAQANAsDqL-Q3AvVEXT9bym5oQm4XKZS5E4iRbq_yOCH-D0lrdUDiECkgSuMHgB8uQvGh1FjcBMlnXK5yQMYjX4VpMk3YPPHaBk_ubeigvtWi3u42Mum58rte2soKvK9BrKPI238izv4Rr3dd3sjDmaExz-Sh9zMi2H</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>CAPACITOR-CONTAINING CHIP CARRIER SUBSTRATE AND ITS MANUFACTURING METHOD</title><source>esp@cenet</source><creator>PATEL CHIRAG SURYAKANT ; ANDRY PAUL STEPHEN</creator><creatorcontrib>PATEL CHIRAG SURYAKANT ; ANDRY PAUL STEPHEN</creatorcontrib><description>PROBLEM TO BE SOLVED: To provide a chip carrier substrate comprising a capacitor aperture and a laterally separated via an aperture each of which is located in a substrate. SOLUTION: The capacitor aperture has a narrower line width and a shallower depth than those of the via aperture to obtain a microloading effect in a plasma etching method that is used for simultaneously etching the capacitor aperture and the via aperture in the substrate. Subsequently a capacitor is formed and located in the capacitor aperture and a via is formed and located in the via apertures. Various combinations of a first capacitor plate layer, a capacitor dielectric layer and a second capacitor plate layer may be obtained continuously with respect to the capacitor aperture and the via aperture. COPYRIGHT: (C)2008,JPO&INPIT</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; CAPACITORS ; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES ORLIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE ; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ; PRINTED CIRCUITS ; SEMICONDUCTOR DEVICES</subject><creationdate>2008</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20080731&DB=EPODOC&CC=JP&NR=2008177576A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20080731&DB=EPODOC&CC=JP&NR=2008177576A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>PATEL CHIRAG SURYAKANT</creatorcontrib><creatorcontrib>ANDRY PAUL STEPHEN</creatorcontrib><title>CAPACITOR-CONTAINING CHIP CARRIER SUBSTRATE AND ITS MANUFACTURING METHOD</title><description>PROBLEM TO BE SOLVED: To provide a chip carrier substrate comprising a capacitor aperture and a laterally separated via an aperture each of which is located in a substrate. SOLUTION: The capacitor aperture has a narrower line width and a shallower depth than those of the via aperture to obtain a microloading effect in a plasma etching method that is used for simultaneously etching the capacitor aperture and the via aperture in the substrate. Subsequently a capacitor is formed and located in the capacitor aperture and a via is formed and located in the via apertures. Various combinations of a first capacitor plate layer, a capacitor dielectric layer and a second capacitor plate layer may be obtained continuously with respect to the capacitor aperture and the via aperture. COPYRIGHT: (C)2008,JPO&INPIT</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CAPACITORS</subject><subject>CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES ORLIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE</subject><subject>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</subject><subject>PRINTED CIRCUITS</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2008</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNyrEKwjAQANAsDqL-Q3AvVEXT9bym5oQm4XKZS5E4iRbq_yOCH-D0lrdUDiECkgSuMHgB8uQvGh1FjcBMlnXK5yQMYjX4VpMk3YPPHaBk_ubeigvtWi3u42Mum58rte2soKvK9BrKPI238izv4Rr3dd3sjDmaExz-Sh9zMi2H</recordid><startdate>20080731</startdate><enddate>20080731</enddate><creator>PATEL CHIRAG SURYAKANT</creator><creator>ANDRY PAUL STEPHEN</creator><scope>EVB</scope></search><sort><creationdate>20080731</creationdate><title>CAPACITOR-CONTAINING CHIP CARRIER SUBSTRATE AND ITS MANUFACTURING METHOD</title><author>PATEL CHIRAG SURYAKANT ; ANDRY PAUL STEPHEN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2008177576A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2008</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CAPACITORS</topic><topic>CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES ORLIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE</topic><topic>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</topic><topic>PRINTED CIRCUITS</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>PATEL CHIRAG SURYAKANT</creatorcontrib><creatorcontrib>ANDRY PAUL STEPHEN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>PATEL CHIRAG SURYAKANT</au><au>ANDRY PAUL STEPHEN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>CAPACITOR-CONTAINING CHIP CARRIER SUBSTRATE AND ITS MANUFACTURING METHOD</title><date>2008-07-31</date><risdate>2008</risdate><abstract>PROBLEM TO BE SOLVED: To provide a chip carrier substrate comprising a capacitor aperture and a laterally separated via an aperture each of which is located in a substrate. SOLUTION: The capacitor aperture has a narrower line width and a shallower depth than those of the via aperture to obtain a microloading effect in a plasma etching method that is used for simultaneously etching the capacitor aperture and the via aperture in the substrate. Subsequently a capacitor is formed and located in the capacitor aperture and a via is formed and located in the via apertures. Various combinations of a first capacitor plate layer, a capacitor dielectric layer and a second capacitor plate layer may be obtained continuously with respect to the capacitor aperture and the via aperture. COPYRIGHT: (C)2008,JPO&INPIT</abstract><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | eng |
| recordid | cdi_epo_espacenet_JP2008177576A |
| source | esp@cenet |
| subjects | BASIC ELECTRIC ELEMENTS CAPACITORS CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES ORLIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ELECTRICITY MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS PRINTED CIRCUITS SEMICONDUCTOR DEVICES |
| title | CAPACITOR-CONTAINING CHIP CARRIER SUBSTRATE AND ITS MANUFACTURING METHOD |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-19T08%3A37%3A36IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=PATEL%20CHIRAG%20SURYAKANT&rft.date=2008-07-31&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EJP2008177576A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |