SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF

PROBLEM TO BE SOLVED: To provide a nonvolatile memory cell technology which reduces coupling capacitance related to a gate electrode for charge accumulation. SOLUTION: On the main surface of a semiconductor substrate 1, a plurality of nonvolatile memory cells constituting a flash memory is formed. E...

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1. Verfasser: ISHIGAKI YOSHIYUKI
Format: Patent
Sprache:eng
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Zusammenfassung:PROBLEM TO BE SOLVED: To provide a nonvolatile memory cell technology which reduces coupling capacitance related to a gate electrode for charge accumulation. SOLUTION: On the main surface of a semiconductor substrate 1, a plurality of nonvolatile memory cells constituting a flash memory is formed. Each of the nonvolatile memory cells comprises an insulating film 2, a floating gate electrode FG formed thereon, an insulating film 10 formed thereon, and a word line WL formed thereon. The floating gate electrode FG is formed of, for example, polysilicon, with a cavity 8b formed therein. Thus, the counter area between adjoining floating gate electrodes FG and that between the floating gate electrode FG and other wiring (for example, plug 22) can be reduced for reduced coupling capacitance related to the floating gate electrode FG, thereby improving the performance and operation reliability of the flash memory. COPYRIGHT: (C)2008,JPO&INPIT