LAYOUT DATA FORMING DEVICE AND LAYOUT DATA FORMING METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

PROBLEM TO BE SOLVED: To provide a semiconductor device with high reliability, high yield and high integration by improving the verification accuracy of a semiconductor integrated circuit. SOLUTION: The device comprises a logic circuit diagram design part for designing a logic circuit diagram based on information for specifications of semiconductor integrated circuit; a layout data forming part for forming layout data based on the logic circuit diagram; a resistance information extraction part for extracting information for resistance of wiring from the layout data; a circuit simulation execution part for executing circuit simulation; a current direction identification part for identifying a current direction in the wiring based on the information for resistance of wiring and the execution result of the circuit simulation; a verification part for verifying, based on information for the current direction in the wiring, whether layout data of the wiring violates a design rule extracted from the information for specifications of semiconductor integrated circuit or not, and generating a verification result; and a data output part for outputting the layout data. COPYRIGHT: (C)2008,JPO&INPIT