SEMICONDUCTOR MEMORY DEVICE

PROBLEM TO BE SOLVED: To provide a semiconductor memory device in which operation reliability can be enhanced. SOLUTION: The device is provided with s memory cell array 10 in which memory cells MC are arranged in a matrix state, word lines WL connecting gates of the memory cells MC, a row decoder 11 applying voltage to the word lines WL, and a voltage generating circuit 17 generating boosting voltage and outputting the boosting voltage as the voltage, the voltage generating circuit 17 is provided with a comparator 20 comparing first voltage Vref with second voltage V1 and outputting a compared result signal CMP, a constant current circuit 23 generating a first control signal OSCED 2 in accordance with the compared result signal CMP output from the comparator 20, a delay circuit 22 generating a second control signal OSCEE by delaying the compared result signal CMP output from the comparator 20, and charge pump circuits 25-0 to 25-3 generating the boosting voltage in accordance with the first, the second control signals OSCED2, OSCEE. COPYRIGHT: (C)2008,JPO&INPIT