VERTICAL DRAM DEVICE EQUIPPED WITH CHANNEL ACCESS TRANSISTOR AND LAYERED ACCUMULATION CAPACITOR AND RELATED METHOD

PROBLEM TO BE SOLVED: To provide a higher-density integrated circuit memory device while maintaining a sufficient capacitance level for an appropriate device operation. SOLUTION: An integrated circuit memory device includes a substrate 22 having at least one internal connection wire 23 and a plurali...

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1. Verfasser: CHOI SEUNGMOO
Format: Patent
Sprache:eng
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Zusammenfassung:PROBLEM TO BE SOLVED: To provide a higher-density integrated circuit memory device while maintaining a sufficient capacitance level for an appropriate device operation. SOLUTION: An integrated circuit memory device includes a substrate 22 having at least one internal connection wire 23 and a plurality of memory cells 20 formed the substrate 22. Each memory cell 20 includes a pillar 40, electrically connected with the connection wire 23, comprising a lower source/drain region 42 for a cell access transistor, upper source/drain region 44 for the same, and at least one channel region 46 extending therebetween in a vertical direction. It further includes an accumulated capacitor adjacent to the upper source/drain 44, the accumulated capacitor comprising a first electrode layer 56, dielectric layer 58, and second electrode layer 60. COPYRIGHT: (C)2008,JPO&INPIT