WAFER EDGE FACE PROTECTIVE DEVICE

PROBLEM TO BE SOLVED: To provide a wafer edge protective device for processing two or more wafers efficiently while preventing processing failure, such as wafer peeling. SOLUTION: By operating a pushing mechanism 43; a wafer pushing unit 25 and a wafer mounting unit 23 are approached, and two wafers...

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description PROBLEM TO BE SOLVED: To provide a wafer edge protective device for processing two or more wafers efficiently while preventing processing failure, such as wafer peeling. SOLUTION: By operating a pushing mechanism 43; a wafer pushing unit 25 and a wafer mounting unit 23 are approached, and two wafers W between the wafer pushing unit 25 and the wafer mounting unit 23 are pinched each by seal members 9, 33 so that two wafers W mounted on the wafer mounting unit 23 are put in a pushed state by the wafer pushing unit 25. In this way, processing failure, such as processing of the edge face of the wafer W by potassium hydroxide, and corroding of wax or the like which bonds the wafer W to a base member, by potassium hydroxide, can be prevented. In addition, if each wafer W is mounted on plural-wafer mounting plate 3, the edge face of two or more wafers W can be protected easily and thereby two or more wafers W are processed effectively. COPYRIGHT: (C)2008,JPO&INPIT
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JP2008004875A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JP2008004875A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JP2008004875A3</originalsourceid><addsrcrecordid>eNrjZFAMd3RzDVJwdXF3VXBzdHZVCAjyD3F1DvEMc1VwcQ3zdHblYWBNS8wpTuWF0twMSm6uIc4euqkF-fGpxQWJyal5qSXxXgFGBgYWBgYmFuamjsZEKQIANb4iTg</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>WAFER EDGE FACE PROTECTIVE DEVICE</title><source>esp@cenet</source><creator>NADA KAZUNARI</creator><creatorcontrib>NADA KAZUNARI</creatorcontrib><description>PROBLEM TO BE SOLVED: To provide a wafer edge protective device for processing two or more wafers efficiently while preventing processing failure, such as wafer peeling. SOLUTION: By operating a pushing mechanism 43; a wafer pushing unit 25 and a wafer mounting unit 23 are approached, and two wafers W between the wafer pushing unit 25 and the wafer mounting unit 23 are pinched each by seal members 9, 33 so that two wafers W mounted on the wafer mounting unit 23 are put in a pushed state by the wafer pushing unit 25. In this way, processing failure, such as processing of the edge face of the wafer W by potassium hydroxide, and corroding of wax or the like which bonds the wafer W to a base member, by potassium hydroxide, can be prevented. In addition, if each wafer W is mounted on plural-wafer mounting plate 3, the edge face of two or more wafers W can be protected easily and thereby two or more wafers W are processed effectively. COPYRIGHT: (C)2008,JPO&amp;INPIT</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; DRESSING OR CONDITIONING OF ABRADING SURFACES ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS ; GRINDING ; MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING ; PERFORMING OPERATIONS ; POLISHING ; SEMICONDUCTOR DEVICES ; TRANSPORTING</subject><creationdate>2008</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20080110&amp;DB=EPODOC&amp;CC=JP&amp;NR=2008004875A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20080110&amp;DB=EPODOC&amp;CC=JP&amp;NR=2008004875A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>NADA KAZUNARI</creatorcontrib><title>WAFER EDGE FACE PROTECTIVE DEVICE</title><description>PROBLEM TO BE SOLVED: To provide a wafer edge protective device for processing two or more wafers efficiently while preventing processing failure, such as wafer peeling. SOLUTION: By operating a pushing mechanism 43; a wafer pushing unit 25 and a wafer mounting unit 23 are approached, and two wafers W between the wafer pushing unit 25 and the wafer mounting unit 23 are pinched each by seal members 9, 33 so that two wafers W mounted on the wafer mounting unit 23 are put in a pushed state by the wafer pushing unit 25. In this way, processing failure, such as processing of the edge face of the wafer W by potassium hydroxide, and corroding of wax or the like which bonds the wafer W to a base member, by potassium hydroxide, can be prevented. In addition, if each wafer W is mounted on plural-wafer mounting plate 3, the edge face of two or more wafers W can be protected easily and thereby two or more wafers W are processed effectively. COPYRIGHT: (C)2008,JPO&amp;INPIT</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>DRESSING OR CONDITIONING OF ABRADING SURFACES</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS</subject><subject>GRINDING</subject><subject>MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING</subject><subject>PERFORMING OPERATIONS</subject><subject>POLISHING</subject><subject>SEMICONDUCTOR DEVICES</subject><subject>TRANSPORTING</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2008</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFAMd3RzDVJwdXF3VXBzdHZVCAjyD3F1DvEMc1VwcQ3zdHblYWBNS8wpTuWF0twMSm6uIc4euqkF-fGpxQWJyal5qSXxXgFGBgYWBgYmFuamjsZEKQIANb4iTg</recordid><startdate>20080110</startdate><enddate>20080110</enddate><creator>NADA KAZUNARI</creator><scope>EVB</scope></search><sort><creationdate>20080110</creationdate><title>WAFER EDGE FACE PROTECTIVE DEVICE</title><author>NADA KAZUNARI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2008004875A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2008</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>DRESSING OR CONDITIONING OF ABRADING SURFACES</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS</topic><topic>GRINDING</topic><topic>MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING</topic><topic>PERFORMING OPERATIONS</topic><topic>POLISHING</topic><topic>SEMICONDUCTOR DEVICES</topic><topic>TRANSPORTING</topic><toplevel>online_resources</toplevel><creatorcontrib>NADA KAZUNARI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>NADA KAZUNARI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>WAFER EDGE FACE PROTECTIVE DEVICE</title><date>2008-01-10</date><risdate>2008</risdate><abstract>PROBLEM TO BE SOLVED: To provide a wafer edge protective device for processing two or more wafers efficiently while preventing processing failure, such as wafer peeling. SOLUTION: By operating a pushing mechanism 43; a wafer pushing unit 25 and a wafer mounting unit 23 are approached, and two wafers W between the wafer pushing unit 25 and the wafer mounting unit 23 are pinched each by seal members 9, 33 so that two wafers W mounted on the wafer mounting unit 23 are put in a pushed state by the wafer pushing unit 25. In this way, processing failure, such as processing of the edge face of the wafer W by potassium hydroxide, and corroding of wax or the like which bonds the wafer W to a base member, by potassium hydroxide, can be prevented. In addition, if each wafer W is mounted on plural-wafer mounting plate 3, the edge face of two or more wafers W can be protected easily and thereby two or more wafers W are processed effectively. COPYRIGHT: (C)2008,JPO&amp;INPIT</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
DRESSING OR CONDITIONING OF ABRADING SURFACES
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
GRINDING
MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING
PERFORMING OPERATIONS
POLISHING
SEMICONDUCTOR DEVICES
TRANSPORTING
title WAFER EDGE FACE PROTECTIVE DEVICE
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-02T00%3A36%3A56IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=NADA%20KAZUNARI&rft.date=2008-01-10&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EJP2008004875A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true