TIMING ANALYSIS METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT

PROBLEM TO BE SOLVED: To provide a timing verification method required in consideration of the difference of variation due to the difference of wiring layers since clock skew is generated when the ways of variation of wiring is different for every wiring layer, and the wiring layers to be used by a clock path are different in a semiconductor integrated circuit. SOLUTION: This image analysis method comprises: a step S11 where it is assumed that the wiring capacity of a clock tree is independently variable for every wiring layer, wiring capacities of clock path with respect to the combination of all ways of variation are calculated; a step S12 where delay times of the clock path with respect to the combination of all ways of variation in a process are calculated; a step S13 where clock skew between a pre-flip flop and a post-flip flop is calculated; a step S14 where the clock skews in a process tojudger that the largest clock skew is a clock skew margin, and calculating the wiring capacity of the data path in a process is calculated; a step S15 where the delay time of the data path in a process is calculated; and a step S16 where a timing verification is performedby using the clock skew margin. COPYRIGHT: (C)2008,JPO&INPIT