PHASE LOCKED LOOP CIRCUIT AND CONTROL METHOD USED BY SAME

PROBLEM TO BE SOLVED: To provide a phase locked loop circuit capable of coping with abnormity of a reference clock even when an abnormality occurs in the reference clock. SOLUTION: A counter 111 receives an external clock signal and generates a rectangular wave signal synchronously with an internal...

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Hauptverfasser: KATO MASAKI, SHIBAGAKI TARO
Format: Patent
Sprache:eng
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Zusammenfassung:PROBLEM TO BE SOLVED: To provide a phase locked loop circuit capable of coping with abnormity of a reference clock even when an abnormality occurs in the reference clock. SOLUTION: A counter 111 receives an external clock signal and generates a rectangular wave signal synchronously with an internal clock signal, a counter 112-2 generates a window signal required for detecting the abnormality of the external clock signal from the internal clock signal, and an abnormality decision control section 114-2 decides whether or not a leading of the rectangular wave signal is within a high level period of the window signal, controls the counter 111 so that the leading of the rectangular wave signal is within the high level period of the window signal when the leading of the rectangular wave signal is not within a high level period of the window signal, and controls ON/OFF of a switch 130, so as to control application of a control voltage to a voltage controlled crystal oscillator 12. COPYRIGHT: (C)2007,JPO&INPIT