SEMICONDUCTOR MEMORY DEVICE

PROBLEM TO BE SOLVED: To reduce current consumption in charging of a bit line after a read/write operation. SOLUTION: An SRAM includes a control circuit 20 and charge circuits 50-0 to 50-n. The control circuit 20 outputs a charge control signal CHL_ and an address AD during reading/writing of data from/to a memory cell MC, and a precharge signal RPC only during reading of data from the memory cell MC. Each charge circuit 50 precharges only a bit line pair BL/BLB of a selection target to be selected by the address AD to a VDD level on the basis of the precharge signal RPC, and charges the bit line pair BL/BLB to maintain a potential VDD-x lower than the VDD level after the data read or write operation. Each charge circuit 50 charges the bit line pair BL/BLB to a fixed potential VDD-x after the read/write operation, but does not charge the pair when a potential exceeds the fixed potential VDD-x. COPYRIGHT: (C)2007,JPO&INPIT