DATA PROCESSOR

PROBLEM TO BE SOLVED: To speed up processing when using a reconfigurable logic circuit by dispensing reconfiguration instruction operation by a CPU for the reconfigurable logic circuit. SOLUTION: A circuit information source 14 monitors an instruction read by a CPU 10 by monitoring an instruction pa...

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1. Verfasser: SHIMADA KEIICHIRO
Format: Patent
Sprache:eng
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Zusammenfassung:PROBLEM TO BE SOLVED: To speed up processing when using a reconfigurable logic circuit by dispensing reconfiguration instruction operation by a CPU for the reconfigurable logic circuit. SOLUTION: A circuit information source 14 monitors an instruction read by a CPU 10 by monitoring an instruction passing through a system bus 11. If the CPU 10 reads a special instruction, notifies the CPU 10 to wait for processing by the reconfigurable logic circuit 15 regarding the specified instruction, and provides the reconfigurable logic circuit 15 with circuit configuration information corresponding to the special instruction. Then, the circuit information source 14, upon receiving a processing termination notice from the reconfigurable logic circuit 15, provides the CPU 10 with an instruction to release a state waiting for special instruction processing by the reconfigurable logic circuit 15. COPYRIGHT: (C)2007,JPO&INPIT