MEMORY BUS LOAD ADJUSTMENT DEVICE

PROBLEM TO BE SOLVED: To provide a memory bus load adjustment device allowing efficient share of a shared memory by efficiently reading data stored in each input side memory and storing them into the shared memory, and efficiently outputting the data stored in the shared memory to an output side memory. SOLUTION: A priority determination circuit part 90 acquires a minimum value of each free capacity from input side monitor part 31-33, acquires a maximum value of each free capacity from each output side monitor part 71-73, outputs a reading priority instruction most preferentially reading the data from the input side memory 21-23 having the smallest minimum value of each free capacity acquired from each input side monitor part 31-33 to a memory arbitration circuit 40, and outputs a writing priority instruction most preferentially writing the data into the output side memory 61-63 having the largest maximum value of each free capacity acquired from each output side monitor part 71-73 to the memory arbitration circuit part 40. COPYRIGHT: (C)2007,JPO&INPIT