PROCESS EVALUATION DEVICE, SEMICONDUCTOR DEVICE THEREWITH, AND EVALUATION METHOD OF SEMICONDUCTOR MANUFACTURING PROCESS USING SAME

PROBLEM TO BE SOLVED: To provide a process evaluation device equipped with evaluation patterns for evaluating correctly the electric stress derived from the potential difference in the wafer surface generated in the process of manufacturing a semiconductor device. SOLUTION: The process evaluation device formed on a semiconductor substrate comprises: a plurality of two-terminal elements 3a and 3b consisting of wiring layers with inspection regions opposing each other while sandwiching an insulating film; and an antenna pattern 5 consisting of two or more conductive patterns having the same antenna ratio which are formed as top layer wiring in a predetermined region of the semiconductor substrate, so that it may be brought into contact with at least one terminal of the two-terminal elements 3a and 3b, respectively. Accordingly, the electric charge induced on the antenna pattern can be detected by the breakdown caused by the voltage rise between the two-terminal element 3a and 3b. COPYRIGHT: (C)2007,JPO&INPIT