SEMICONDUCTOR INTEGRATED CIRCUIT

PROBLEM TO BE SOLVED: To obtain a semiconductor integrated circuit constituted of a plurality of basic cells and capable of supplying a plurality of sorts of power without reducing the degree of integration. SOLUTION: In each of basic cells 1 formed on an SOI (Silicon-ON-Insulator) substrate, an n-t...

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Bibliographische Detailangaben
Hauptverfasser: OBAYASHI MASAYUKI, NISHIMAKI HIDEKATSU
Format: Patent
Sprache:eng
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Zusammenfassung:PROBLEM TO BE SOLVED: To obtain a semiconductor integrated circuit constituted of a plurality of basic cells and capable of supplying a plurality of sorts of power without reducing the degree of integration. SOLUTION: In each of basic cells 1 formed on an SOI (Silicon-ON-Insulator) substrate, an n-type diffusion area 12 is formed in a part of an n well area 8 in which a PMOS (P-channel Metal-Oxide Semiconductor) transistor is formed and a VDD power supply wire 11 is formed on the n-type diffusion area 12 so as to be electrically connected. A p-type diffusion area 17 is formed in a part of a p well area 9 in which an NMOS (N-channel Metal-Oxide Semiconductor) transistor is formed and a GND power supply wire 16 is formed on the p-type diffusion area 17 so as to be electrically connected. The VDD power supply wire 11 and the GND power supply wire 16 are formed in the basic cell 1 at a prescribed distance without being brought into contact with a cell boundary 10 of the basis cell 1. The n-type diffusion area 12 and the p-type diffusion area 17 correspond to body contact areas for setting the back gate potential levels of the PMOS transistor and the NMOS transistor. COPYRIGHT: (C)2007,JPO&INPIT