RELIABILITY EVALUATION METHOD FOR SEMICONDUCTOR DEVICE

PROBLEM TO BE SOLVED: To allow a high-precision lifetime forecast for micro transistors such as an SOS (Silicon on Sapphire) and an FET and a guarantee on an increase in a drain current. SOLUTION: The reliability evaluation method, in a first step, measures a drain current Ids when a stress drain vo...

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1. Verfasser: FURUHIRA TAKAAKI
Format: Patent
Sprache:eng
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Zusammenfassung:PROBLEM TO BE SOLVED: To allow a high-precision lifetime forecast for micro transistors such as an SOS (Silicon on Sapphire) and an FET and a guarantee on an increase in a drain current. SOLUTION: The reliability evaluation method, in a first step, measures a drain current Ids when a stress drain voltage is applied to the SOS or FET for each stress time, wherein the stress drain voltage, which is higher than a power supply voltage driving the FET and is lower than the breakdown voltage of the FET, is provided to a gate. In a second step, a drain current maximum value Idsmax is estimated through the measured drain current Ids and the stress time. In a third step, the relationship between the amount of change ΔIds of the drain current Ids and the stress time is plotted on a double logarithmic graph with the drain current maximum value Idsmax as a standard. In a fourth step, a hot carrier lifetime is estimated by drawing an approximate line 24-2 on the plotted graph. COPYRIGHT: (C)2007,JPO&INPIT