PLL CIRCUIT

PROBLEM TO BE SOLVED: To provide a PLL (Phase-Locked Loop) circuit capable of flexibly coping with a difference in a jitter environment or characteristics of a voltage control oscillator, by easily changing the parameter of a gradient of voltage control in response to the difference in the jitter en...

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Bibliographische Detailangaben
Hauptverfasser: HOSOI TOSHIO, UEDA HISAO, AGENO YUZO, OOTSUKA TATSUSHI
Format: Patent
Sprache:eng
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Beschreibung
Zusammenfassung:PROBLEM TO BE SOLVED: To provide a PLL (Phase-Locked Loop) circuit capable of flexibly coping with a difference in a jitter environment or characteristics of a voltage control oscillator, by easily changing the parameter of a gradient of voltage control in response to the difference in the jitter environment or the characteristics of the voltage control oscillator. SOLUTION: A frequency divider 10 divides an input clock CLK_A. A frequency divider 11 divides an output clock CLK_B. A phase comparison part 12 holds a phase difference between a dividing clock CLK_a outputted by the frequency divider 10 and a dividing clock CLK_b outputted by the frequency divider 11 as a phase comparison result. A software processing part 13 carries out soft processing of the phase comparison result, and outputs a pulse train CP for generating a control voltage. A loop filter 14 gives a control voltage VC which smoothes the pulse train CP for generating a control voltage to the voltage control oscillator 15, and the voltage control oscillator 15 outputs the output clock CLK_B of the frequency corresponding to the control voltage VC. COPYRIGHT: (C)2007,JPO&INPIT