SEMICONDUCTOR INTEGRATED CIRCUIT APPARATUS

PROBLEM TO BE SOLVED: To prevent excessive erasing of memory cells and to reduce largely deterioration and disturbance of memory cells, in multi-bank erasing. SOLUTION: In multi-bank erasing operation of a nonvolatile semiconductor memory, a verify pass signal VP of a Hi level is output from a bank...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: MATSUSHITA TORU, MUKODA HIDEFUMI, OTA TAKESHI
Format: Patent
Sprache:eng
Schlagworte:
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator MATSUSHITA TORU
MUKODA HIDEFUMI
OTA TAKESHI
description PROBLEM TO BE SOLVED: To prevent excessive erasing of memory cells and to reduce largely deterioration and disturbance of memory cells, in multi-bank erasing. SOLUTION: In multi-bank erasing operation of a nonvolatile semiconductor memory, a verify pass signal VP of a Hi level is output from a bank selecting part 19 at the time of erasing bias. Successively, erasing verify is finished, when erasing-verify of an arbitrary bank is passed out of banks Bank 0 to Bank 3, a controller outputs a sub-decoder control signal Csub to a bank selecting part 19 corresponding to a bank in which erasing-verify is passed (e.g. shifting from a Hi level to a Lo level). Thereby, the verify pass signal VP output from the bank selecting part 19 is reversed. Receiving this, a main decoder circuit 20 makes a word line in the bank in which erasing-verify is passed a whole non-selection state. COPYRIGHT: (C)2007,JPO&INPIT
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JP2007066406A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JP2007066406A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JP2007066406A3</originalsourceid><addsrcrecordid>eNrjZNAKdvX1dPb3cwl1DvEPUvD0C3F1D3IMcXVRcPYMcg71DFFwDAhwBIqEBvMwsKYl5hSn8kJpbgYlN9cQZw_d1IL8-NTigsTk1LzUknivACMDA3MDMzMTAzNHY6IUAQDADCVt</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>SEMICONDUCTOR INTEGRATED CIRCUIT APPARATUS</title><source>esp@cenet</source><creator>MATSUSHITA TORU ; MUKODA HIDEFUMI ; OTA TAKESHI</creator><creatorcontrib>MATSUSHITA TORU ; MUKODA HIDEFUMI ; OTA TAKESHI</creatorcontrib><description>PROBLEM TO BE SOLVED: To prevent excessive erasing of memory cells and to reduce largely deterioration and disturbance of memory cells, in multi-bank erasing. SOLUTION: In multi-bank erasing operation of a nonvolatile semiconductor memory, a verify pass signal VP of a Hi level is output from a bank selecting part 19 at the time of erasing bias. Successively, erasing verify is finished, when erasing-verify of an arbitrary bank is passed out of banks Bank 0 to Bank 3, a controller outputs a sub-decoder control signal Csub to a bank selecting part 19 corresponding to a bank in which erasing-verify is passed (e.g. shifting from a Hi level to a Lo level). Thereby, the verify pass signal VP output from the bank selecting part 19 is reversed. Receiving this, a main decoder circuit 20 makes a word line in the bank in which erasing-verify is passed a whole non-selection state. COPYRIGHT: (C)2007,JPO&amp;INPIT</description><language>eng</language><subject>INFORMATION STORAGE ; PHYSICS ; STATIC STORES</subject><creationdate>2007</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20070315&amp;DB=EPODOC&amp;CC=JP&amp;NR=2007066406A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20070315&amp;DB=EPODOC&amp;CC=JP&amp;NR=2007066406A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>MATSUSHITA TORU</creatorcontrib><creatorcontrib>MUKODA HIDEFUMI</creatorcontrib><creatorcontrib>OTA TAKESHI</creatorcontrib><title>SEMICONDUCTOR INTEGRATED CIRCUIT APPARATUS</title><description>PROBLEM TO BE SOLVED: To prevent excessive erasing of memory cells and to reduce largely deterioration and disturbance of memory cells, in multi-bank erasing. SOLUTION: In multi-bank erasing operation of a nonvolatile semiconductor memory, a verify pass signal VP of a Hi level is output from a bank selecting part 19 at the time of erasing bias. Successively, erasing verify is finished, when erasing-verify of an arbitrary bank is passed out of banks Bank 0 to Bank 3, a controller outputs a sub-decoder control signal Csub to a bank selecting part 19 corresponding to a bank in which erasing-verify is passed (e.g. shifting from a Hi level to a Lo level). Thereby, the verify pass signal VP output from the bank selecting part 19 is reversed. Receiving this, a main decoder circuit 20 makes a word line in the bank in which erasing-verify is passed a whole non-selection state. COPYRIGHT: (C)2007,JPO&amp;INPIT</description><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2007</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNAKdvX1dPb3cwl1DvEPUvD0C3F1D3IMcXVRcPYMcg71DFFwDAhwBIqEBvMwsKYl5hSn8kJpbgYlN9cQZw_d1IL8-NTigsTk1LzUknivACMDA3MDMzMTAzNHY6IUAQDADCVt</recordid><startdate>20070315</startdate><enddate>20070315</enddate><creator>MATSUSHITA TORU</creator><creator>MUKODA HIDEFUMI</creator><creator>OTA TAKESHI</creator><scope>EVB</scope></search><sort><creationdate>20070315</creationdate><title>SEMICONDUCTOR INTEGRATED CIRCUIT APPARATUS</title><author>MATSUSHITA TORU ; MUKODA HIDEFUMI ; OTA TAKESHI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2007066406A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2007</creationdate><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>MATSUSHITA TORU</creatorcontrib><creatorcontrib>MUKODA HIDEFUMI</creatorcontrib><creatorcontrib>OTA TAKESHI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>MATSUSHITA TORU</au><au>MUKODA HIDEFUMI</au><au>OTA TAKESHI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SEMICONDUCTOR INTEGRATED CIRCUIT APPARATUS</title><date>2007-03-15</date><risdate>2007</risdate><abstract>PROBLEM TO BE SOLVED: To prevent excessive erasing of memory cells and to reduce largely deterioration and disturbance of memory cells, in multi-bank erasing. SOLUTION: In multi-bank erasing operation of a nonvolatile semiconductor memory, a verify pass signal VP of a Hi level is output from a bank selecting part 19 at the time of erasing bias. Successively, erasing verify is finished, when erasing-verify of an arbitrary bank is passed out of banks Bank 0 to Bank 3, a controller outputs a sub-decoder control signal Csub to a bank selecting part 19 corresponding to a bank in which erasing-verify is passed (e.g. shifting from a Hi level to a Lo level). Thereby, the verify pass signal VP output from the bank selecting part 19 is reversed. Receiving this, a main decoder circuit 20 makes a word line in the bank in which erasing-verify is passed a whole non-selection state. COPYRIGHT: (C)2007,JPO&amp;INPIT</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_JP2007066406A
source esp@cenet
subjects INFORMATION STORAGE
PHYSICS
STATIC STORES
title SEMICONDUCTOR INTEGRATED CIRCUIT APPARATUS
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-03T00%3A21%3A38IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=MATSUSHITA%20TORU&rft.date=2007-03-15&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EJP2007066406A%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true