SEMICONDUCTOR INTEGRATED CIRCUIT APPARATUS

PROBLEM TO BE SOLVED: To prevent excessive erasing of memory cells and to reduce largely deterioration and disturbance of memory cells, in multi-bank erasing. SOLUTION: In multi-bank erasing operation of a nonvolatile semiconductor memory, a verify pass signal VP of a Hi level is output from a bank...

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Bibliographische Detailangaben
Hauptverfasser: MATSUSHITA TORU, MUKODA HIDEFUMI, OTA TAKESHI
Format: Patent
Sprache:eng
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Zusammenfassung:PROBLEM TO BE SOLVED: To prevent excessive erasing of memory cells and to reduce largely deterioration and disturbance of memory cells, in multi-bank erasing. SOLUTION: In multi-bank erasing operation of a nonvolatile semiconductor memory, a verify pass signal VP of a Hi level is output from a bank selecting part 19 at the time of erasing bias. Successively, erasing verify is finished, when erasing-verify of an arbitrary bank is passed out of banks Bank 0 to Bank 3, a controller outputs a sub-decoder control signal Csub to a bank selecting part 19 corresponding to a bank in which erasing-verify is passed (e.g. shifting from a Hi level to a Lo level). Thereby, the verify pass signal VP output from the bank selecting part 19 is reversed. Receiving this, a main decoder circuit 20 makes a word line in the bank in which erasing-verify is passed a whole non-selection state. COPYRIGHT: (C)2007,JPO&INPIT