PIN LAYOUT VERIFICATION SUPPORT SYSTEM

PROBLEM TO BE SOLVED: To shorten the generation time of a pin layout and to reduce the man-hours for return due to errors in scribing, etc., in manual generation concerning a pin layout verification support system. SOLUTION: An automatic generation program 1-1 automatically generates circuit descrip...

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Hauptverfasser:	SHIRAISHI HIROAKI, TANDA KOICHI, KOHARA YOSHIKATSU, SOEJIMA YOSHINORI
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY PHYSICS SEMICONDUCTOR DEVICES
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creator	SHIRAISHI HIROAKI TANDA KOICHI KOHARA YOSHIKATSU SOEJIMA YOSHINORI
description	PROBLEM TO BE SOLVED: To shorten the generation time of a pin layout and to reduce the man-hours for return due to errors in scribing, etc., in manual generation concerning a pin layout verification support system. SOLUTION: An automatic generation program 1-1 automatically generates circuit description data for verification (RTL) 1-13 and a restriction file 1-14 for implement, based on pin information files 1-11 and setting files 1-12 that are input externally and device information 1-21 and macro information 1-22 that are stored as various databases 1-2. A logical synthesis/layout part 1-3 performs the synthesis/layout of a logical circuit, based on the circuit description data for verification (RTL) 1-13 and the restriction file 1-14 for implement, so as to store the output result data and to output a result report 1-4. COPYRIGHT: (C)2007,JPO&INPIT
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fullrecord	<record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JP2007041984A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JP2007041984A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JP2007041984A3</originalsourceid><addsrcrecordid>eNrjZFAL8PRT8HGM9A8NUQhzDfJ083R2DPH091MIDg0I8A8KUQiODA5x9eVhYE1LzClO5YXS3AxKbq4hzh66qQX58anFBYnJqXmpJfFeAUYGBuYGJoaWFiaOxkQpAgA1ACRx</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>PIN LAYOUT VERIFICATION SUPPORT SYSTEM</title><source>esp@cenet</source><creator>SHIRAISHI HIROAKI ; TANDA KOICHI ; KOHARA YOSHIKATSU ; SOEJIMA YOSHINORI</creator><creatorcontrib>SHIRAISHI HIROAKI ; TANDA KOICHI ; KOHARA YOSHIKATSU ; SOEJIMA YOSHINORI</creatorcontrib><description>PROBLEM TO BE SOLVED: To shorten the generation time of a pin layout and to reduce the man-hours for return due to errors in scribing, etc., in manual generation concerning a pin layout verification support system. SOLUTION: An automatic generation program 1-1 automatically generates circuit description data for verification (RTL) 1-13 and a restriction file 1-14 for implement, based on pin information files 1-11 and setting files 1-12 that are input externally and device information 1-21 and macro information 1-22 that are stored as various databases 1-2. A logical synthesis/layout part 1-3 performs the synthesis/layout of a logical circuit, based on the circuit description data for verification (RTL) 1-13 and the restriction file 1-14 for implement, so as to store the output result data and to output a result report 1-4. COPYRIGHT: (C)2007,JPO&INPIT</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; PHYSICS ; SEMICONDUCTOR DEVICES</subject><creationdate>2007</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20070215&DB=EPODOC&CC=JP&NR=2007041984A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20070215&DB=EPODOC&CC=JP&NR=2007041984A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>SHIRAISHI HIROAKI</creatorcontrib><creatorcontrib>TANDA KOICHI</creatorcontrib><creatorcontrib>KOHARA YOSHIKATSU</creatorcontrib><creatorcontrib>SOEJIMA YOSHINORI</creatorcontrib><title>PIN LAYOUT VERIFICATION SUPPORT SYSTEM</title><description>PROBLEM TO BE SOLVED: To shorten the generation time of a pin layout and to reduce the man-hours for return due to errors in scribing, etc., in manual generation concerning a pin layout verification support system. SOLUTION: An automatic generation program 1-1 automatically generates circuit description data for verification (RTL) 1-13 and a restriction file 1-14 for implement, based on pin information files 1-11 and setting files 1-12 that are input externally and device information 1-21 and macro information 1-22 that are stored as various databases 1-2. A logical synthesis/layout part 1-3 performs the synthesis/layout of a logical circuit, based on the circuit description data for verification (RTL) 1-13 and the restriction file 1-14 for implement, so as to store the output result data and to output a result report 1-4. COPYRIGHT: (C)2007,JPO&INPIT</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>PHYSICS</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2007</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFAL8PRT8HGM9A8NUQhzDfJ083R2DPH091MIDg0I8A8KUQiODA5x9eVhYE1LzClO5YXS3AxKbq4hzh66qQX58anFBYnJqXmpJfFeAUYGBuYGJoaWFiaOxkQpAgA1ACRx</recordid><startdate>20070215</startdate><enddate>20070215</enddate><creator>SHIRAISHI HIROAKI</creator><creator>TANDA KOICHI</creator><creator>KOHARA YOSHIKATSU</creator><creator>SOEJIMA YOSHINORI</creator><scope>EVB</scope></search><sort><creationdate>20070215</creationdate><title>PIN LAYOUT VERIFICATION SUPPORT SYSTEM</title><author>SHIRAISHI HIROAKI ; TANDA KOICHI ; KOHARA YOSHIKATSU ; SOEJIMA YOSHINORI</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2007041984A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2007</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>PHYSICS</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>SHIRAISHI HIROAKI</creatorcontrib><creatorcontrib>TANDA KOICHI</creatorcontrib><creatorcontrib>KOHARA YOSHIKATSU</creatorcontrib><creatorcontrib>SOEJIMA YOSHINORI</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>SHIRAISHI HIROAKI</au><au>TANDA KOICHI</au><au>KOHARA YOSHIKATSU</au><au>SOEJIMA YOSHINORI</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>PIN LAYOUT VERIFICATION SUPPORT SYSTEM</title><date>2007-02-15</date><risdate>2007</risdate><abstract>PROBLEM TO BE SOLVED: To shorten the generation time of a pin layout and to reduce the man-hours for return due to errors in scribing, etc., in manual generation concerning a pin layout verification support system. SOLUTION: An automatic generation program 1-1 automatically generates circuit description data for verification (RTL) 1-13 and a restriction file 1-14 for implement, based on pin information files 1-11 and setting files 1-12 that are input externally and device information 1-21 and macro information 1-22 that are stored as various databases 1-2. A logical synthesis/layout part 1-3 performs the synthesis/layout of a logical circuit, based on the circuit description data for verification (RTL) 1-13 and the restriction file 1-14 for implement, so as to store the output result data and to output a result report 1-4. COPYRIGHT: (C)2007,JPO&INPIT</abstract><oa>free_for_read</oa></addata></record>
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recordid	cdi_epo_espacenet_JP2007041984A
source	esp@cenet
subjects	BASIC ELECTRIC ELEMENTS CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY PHYSICS SEMICONDUCTOR DEVICES
title	PIN LAYOUT VERIFICATION SUPPORT SYSTEM
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