PIN LAYOUT VERIFICATION SUPPORT SYSTEM

PROBLEM TO BE SOLVED: To shorten the generation time of a pin layout and to reduce the man-hours for return due to errors in scribing, etc., in manual generation concerning a pin layout verification support system. SOLUTION: An automatic generation program 1-1 automatically generates circuit description data for verification (RTL) 1-13 and a restriction file 1-14 for implement, based on pin information files 1-11 and setting files 1-12 that are input externally and device information 1-21 and macro information 1-22 that are stored as various databases 1-2. A logical synthesis/layout part 1-3 performs the synthesis/layout of a logical circuit, based on the circuit description data for verification (RTL) 1-13 and the restriction file 1-14 for implement, so as to store the output result data and to output a result report 1-4. COPYRIGHT: (C)2007,JPO&INPIT