METHOD AND SYSTEM FOR CLOCK CIRCUIT

PROBLEM TO BE SOLVED: To provide a circuit capable of reducing part of frequencies of a clock signal supplied to a semiconductor. SOLUTION: A counter circuit 120 for operating so as to output a counter signal 122 with a set of time intervals, and a gate circuit 110 for operating so as to generate an...

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1. Verfasser:	HIMENO TOSHIHIKO
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRONIC CIRCUITRY CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY PHYSICS PULSE TECHNIQUE
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creator	HIMENO TOSHIHIKO
description	PROBLEM TO BE SOLVED: To provide a circuit capable of reducing part of frequencies of a clock signal supplied to a semiconductor. SOLUTION: A counter circuit 120 for operating so as to output a counter signal 122 with a set of time intervals, and a gate circuit 110 for operating so as to generate an output clock signal 114 are provided. The output clock signal 114 is substantially the same as an input clock signal 112 in a first operating mode, and substantially equals the input clock signal 112 in at least one time interval of the pair of time intervals in a second operating mode. COPYRIGHT: (C)2007,JPO&INPIT
format	Patent
fullrecord	<record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_JP2007026447A</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>JP2007026447A</sourcerecordid><originalsourceid>FETCH-epo_espacenet_JP2007026447A3</originalsourceid><addsrcrecordid>eNrjZFD2dQ3x8HdRcPRzUQiODA5x9VVw8w9ScPbxd_ZWcPYMcg71DOFhYE1LzClO5YXS3AxKbq4hzh66qQX58anFBYnJqXmpJfFeAUYGBuYGRmYmJuaOxkQpAgCLHSL9</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>METHOD AND SYSTEM FOR CLOCK CIRCUIT</title><source>esp@cenet</source><creator>HIMENO TOSHIHIKO</creator><creatorcontrib>HIMENO TOSHIHIKO</creatorcontrib><description>PROBLEM TO BE SOLVED: To provide a circuit capable of reducing part of frequencies of a clock signal supplied to a semiconductor. SOLUTION: A counter circuit 120 for operating so as to output a counter signal 122 with a set of time intervals, and a gate circuit 110 for operating so as to generate an output clock signal 114 are provided. The output clock signal 114 is substantially the same as an input clock signal 112 in a first operating mode, and substantially equals the input clock signal 112 in at least one time interval of the pair of time intervals in a second operating mode. COPYRIGHT: (C)2007,JPO&INPIT</description><language>eng</language><subject>BASIC ELECTRONIC CIRCUITRY ; CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; ELECTRICITY ; PHYSICS ; PULSE TECHNIQUE</subject><creationdate>2007</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20070201&DB=EPODOC&CC=JP&NR=2007026447A$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76289</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20070201&DB=EPODOC&CC=JP&NR=2007026447A$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>HIMENO TOSHIHIKO</creatorcontrib><title>METHOD AND SYSTEM FOR CLOCK CIRCUIT</title><description>PROBLEM TO BE SOLVED: To provide a circuit capable of reducing part of frequencies of a clock signal supplied to a semiconductor. SOLUTION: A counter circuit 120 for operating so as to output a counter signal 122 with a set of time intervals, and a gate circuit 110 for operating so as to generate an output clock signal 114 are provided. The output clock signal 114 is substantially the same as an input clock signal 112 in a first operating mode, and substantially equals the input clock signal 112 in at least one time interval of the pair of time intervals in a second operating mode. COPYRIGHT: (C)2007,JPO&INPIT</description><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>ELECTRICITY</subject><subject>PHYSICS</subject><subject>PULSE TECHNIQUE</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2007</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFD2dQ3x8HdRcPRzUQiODA5x9VVw8w9ScPbxd_ZWcPYMcg71DOFhYE1LzClO5YXS3AxKbq4hzh66qQX58anFBYnJqXmpJfFeAUYGBuYGRmYmJuaOxkQpAgCLHSL9</recordid><startdate>20070201</startdate><enddate>20070201</enddate><creator>HIMENO TOSHIHIKO</creator><scope>EVB</scope></search><sort><creationdate>20070201</creationdate><title>METHOD AND SYSTEM FOR CLOCK CIRCUIT</title><author>HIMENO TOSHIHIKO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_JP2007026447A3</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2007</creationdate><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>ELECTRICITY</topic><topic>PHYSICS</topic><topic>PULSE TECHNIQUE</topic><toplevel>online_resources</toplevel><creatorcontrib>HIMENO TOSHIHIKO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>HIMENO TOSHIHIKO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>METHOD AND SYSTEM FOR CLOCK CIRCUIT</title><date>2007-02-01</date><risdate>2007</risdate><abstract>PROBLEM TO BE SOLVED: To provide a circuit capable of reducing part of frequencies of a clock signal supplied to a semiconductor. SOLUTION: A counter circuit 120 for operating so as to output a counter signal 122 with a set of time intervals, and a gate circuit 110 for operating so as to generate an output clock signal 114 are provided. The output clock signal 114 is substantially the same as an input clock signal 112 in a first operating mode, and substantially equals the input clock signal 112 in at least one time interval of the pair of time intervals in a second operating mode. COPYRIGHT: (C)2007,JPO&INPIT</abstract><oa>free_for_read</oa></addata></record>
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subjects	BASIC ELECTRONIC CIRCUITRY CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY PHYSICS PULSE TECHNIQUE
title	METHOD AND SYSTEM FOR CLOCK CIRCUIT
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