METHOD AND SYSTEM FOR CLOCK CIRCUIT

PROBLEM TO BE SOLVED: To provide a circuit capable of reducing part of frequencies of a clock signal supplied to a semiconductor. SOLUTION: A counter circuit 120 for operating so as to output a counter signal 122 with a set of time intervals, and a gate circuit 110 for operating so as to generate an output clock signal 114 are provided. The output clock signal 114 is substantially the same as an input clock signal 112 in a first operating mode, and substantially equals the input clock signal 112 in at least one time interval of the pair of time intervals in a second operating mode. COPYRIGHT: (C)2007,JPO&INPIT