FET BIAS CIRCUIT

PROBLEM TO BE SOLVED: To provide an FET bias circuit capable of applying a bias voltage which need not be adjusted individually to an FET for amplification of an FET amplifying circuit. SOLUTION: The FET bias circuit is equipped with: a monitoring FET in which a gate is connected to the gate for an...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: YODA TAMAKI, OKATOME KENJIRO, SAKAMOTO HIROTOKU
Format: Patent
Sprache:eng
Schlagworte:
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Beschreibung
Zusammenfassung:PROBLEM TO BE SOLVED: To provide an FET bias circuit capable of applying a bias voltage which need not be adjusted individually to an FET for amplification of an FET amplifying circuit. SOLUTION: The FET bias circuit is equipped with: a monitoring FET in which a gate is connected to the gate for an amplifying FET and a source is connected to a source for the amplifying FET, and a drain current corresponding to a bias voltage is nearly in proportion to a drain current of the amplifying FET; and a constant bias circuit which applies the bias voltage placing the FET for amplification in a specified operation class by applying the bias voltage to the monitoring FET so that a drain current flowing to the monitoring FET has the specified operation class. COPYRIGHT: (C)2007,JPO&INPIT