INTEGRATED VERIFICATION AND MANUFACTURABILITY TOOL

INTEGRATED VERIFICATION AND MANUFACTURABILITY TOOL

PROBLEM TO BE SOLVED: To provide an integrated verification and manufacturability tool that provides more efficient verification of integrated device designs. SOLUTION: This verification uses several different verification tools. The integrated verification and manufacturability tool includes a hier...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: GRODD LAURENCE W, YOU SIQIONG, SAHOURIA EMILE, ANDERSON LEIGH C, COBB NICOLAS B
Format: Patent
Sprache:eng
Schlagworte:
APPARATUS SPECIALLY ADAPTED THEREFOR
APPLICATIONS OF SCANNING-PROBE TECHNIQUES, e.g. SCANNING PROBEMICROSCOPY [SPM]
CALCULATING
CINEMATOGRAPHY
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
ELECTROGRAPHY
HOLOGRAPHY
MATERIALS THEREFOR
MEASURING
ORIGINALS THEREFOR
PHOTOGRAPHY
PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES,e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTORDEVICES
PHYSICS
SCANNING-PROBE TECHNIQUES OR APPARATUS
TESTING
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Beschreibung
Zusammenfassung:PROBLEM TO BE SOLVED: To provide an integrated verification and manufacturability tool that provides more efficient verification of integrated device designs. SOLUTION: This verification uses several different verification tools. The integrated verification and manufacturability tool includes a hierarchical database to store design data accessed by a plurality of verification tool components (e.g., layout versus schematic 440, design rule check 450, optical process correction 430, and phase shift mask assignment 420). A checking component includes a layout versus schematic (LVS) component. COPYRIGHT: (C)2007,JPO&INPIT