METHOD FOR FORMING SEMICONDUCTOR DEVICE AND ITS STRUCTURE

METHOD FOR FORMING SEMICONDUCTOR DEVICE AND ITS STRUCTURE

PROBLEM TO BE SOLVED: To minimize misalignment vias penetrating an air gap when the air gap is formed. SOLUTION: Dummy features (48a, 48b) are formed within an interlaminar dielectric layer (36). In one embodiment, a non-gap filling dielectric layer (72) is formed over the dummy features to form voi...

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Hauptverfasser: SOLOMENTSEV YURI E, SMITH BRADLEY P, YU KATHLEEN C, FILIPIAK STANLEY M, SPARKS TERRY G, STROZEWSKI KIRK J, FLAKE JOHN C, GOLDBERG CINDY K, LII YEONG-JYH T
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Zusammenfassung:PROBLEM TO BE SOLVED: To minimize misalignment vias penetrating an air gap when the air gap is formed. SOLUTION: Dummy features (48a, 48b) are formed within an interlaminar dielectric layer (36). In one embodiment, a non-gap filling dielectric layer (72) is formed over the dummy features to form voids (74) between the dummy features or a dummy feature and a current-conducting region (44). In one embodiment, passivation layers (32, 54) are formed by electroless deposition to protect the underlying conductive regions (44, 48a, 48b, 30) from being penetrated from the air gaps (74). Additionally, the passivation layers overhangs the underlying conductive regions, thereby defining dummy features adjacent to the conductive regions. The passivation layers can be formed without an additional patterning step and minimize the misalignment vias penetrating the air gap. COPYRIGHT: (C)2007,JPO&INPIT